IP Library Granted Patent US 11,355,341
Granted Patent B2
US 11,355,341 · App. 16/861,615 · Granted Jun 7, 2022

Semiconductor device and method for supporting ultra-thin semiconductor die

Inventors: Gordon M. Grivna (Mesa, AZ); Stephen St. Germain (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/02381H01L21/0254H01L21/4825H01L21/78H01L23/145H01L23/15H01L23/49562H01L23/49827H01L23/49838H01L23/49844H01L29/2003H01L2224/48247H01L2224/49171
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Quick Facts
Patent No.
US 11,355,341
App. No.
16/861,615
Granted
Jun 7, 2022
Kind
B2
Abstract

A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Claims (32)

1. A semiconductor device, comprising:

a semiconductor die comprising a first semiconductor material, a second semiconductor material directly coupled to the first semiconductor material, and a first conductive layer directly coupled to the second semiconductor material;

an interconnect structure including a die attach area, wherein the semiconductor die is coupled over the die attach area;

a second conductive layer comprised in the interconnect structure;

an insulating layer over the second conductive layer with a first opening in the insulating layer within the die attach area and a second opening in the insulating layer outside the die attach area; and

a conductive material coupled between and directly to both the first conductive layer and the second conductive layer;

wherein the second semiconductor material comprises one of gallium nitride or aluminum gallium nitride.

2. The semiconductor device of claim 1 , wherein the first semiconductor material includes silicon.

3. The semiconductor device of claim 1 , further including an underfill material deposited between the semiconductor die and the die attach area.

4. The semiconductor device of claim 1 , wherein the interconnect structure includes an active device.

5. The semiconductor device of claim 1 , wherein the interconnect structure includes a leadframe.

6. The semiconductor device of claim 1 , further including a protective layer formed over the semiconductor die.

7. The semiconductor device of claim 1 , further including a conductive via formed through the interconnect structure coupled with the semiconductor die.

8. A semiconductor device, comprising:

a semiconductor die comprising a first semiconductor material and a second semiconductor material formed on the first semiconductor material;

an interconnect structure coupled to the semiconductor die, the interconnect structure comprising a conductive layer and a die attach area; and

an insulating layer over the conductive layer with a first opening in the insulating layer within the die attach area and a second opening in the insulating layer outside the die attach area;

wherein the conductive layer extends beyond and out from under a perimeter of the semiconductor die coupled over the die attach area; and

wherein the second semiconductor material comprises gallium nitride or aluminum gallium nitride.

9. The semiconductor device of claim 8 , wherein the first semiconductor material includes silicon.

10. The semiconductor device of claim 8 , further comprising one of a clip or a bond wire coupled with the interconnect structure.

11. The semiconductor device of claim 8 , further including an underfill material deposited between the semiconductor die and the die attach area of the interconnect structure.

12. The semiconductor device of claim 8 , wherein the interconnect structure includes an active device.

13. The semiconductor device of claim 8 , wherein the interconnect structure includes a leadframe.

14. The semiconductor device of claim 8 , further including a protective layer formed over the semiconductor die.

15. The semiconductor device of claim 8 , further including a conductive via formed through the interconnect structure under the semiconductor die.

16. A semiconductor device, comprising:

a semiconductor die comprising a first semiconductor material, one of gallium nitride or aluminum gallium nitride formed on the first semiconductor material, and a first conductive layer directly coupled to the one of gallium nitride or aluminum gallium nitride;

an interconnect structure coupled to the semiconductor die, the interconnect structure comprising a second conductive layer; and

an insulating layer coupled over the second conductive layer with a first opening in the insulating layer within a die attach area and a second opening in the insulating layer outside the die attach area;

wherein the first conductive layer and the second conductive layer are coupled through a conductive material.

17. The semiconductor device of claim 16 , wherein an active device coupled with the die attach area and the semiconductor die are in a cascode configuration.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 053613, FRAME 0621 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0942 →
SECURITY INTEREST Recorded Aug 27, 2020
From: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 053613/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2020
From: GRIVNA, GORDON M.; ST. GERMAIN, STEPHEN
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 052524/0893 →
Continuity (3)
Continuation 16144750 · Sep 27, 2018
Division 15446281 · Mar 1, 2017
Related Publication 20200258739A1 · Aug 13, 2020