IP Library Granted Patent US 10,957,597
Granted Patent B2
US 10,957,597 · App. 16/867,836 · Granted Mar 23, 2021

Semiconductor substrate die sawing singulation systems and methods

Inventor: Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L21/78H01L21/0445
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Quick Facts
Patent No.
US 10,957,597
App. No.
16/867,836
Granted
Mar 23, 2021
Kind
B2
Abstract

Implementations of methods of cutting a semiconductor substrate may include aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate coupled with a backmetal layer and cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate. The method may also include aligning a second saw blade substantially perpendicularly with the semiconductor substrate and cutting entirely through the semiconductor substrate and the backmetal layer using the second saw blade.

Claims (32)

1. A method for cutting a semiconductor substrate comprising:

aligning a first saw blade substantially perpendicularly with a crystal plane of a non-cubic crystalline lattice of a semiconductor substrate;

cutting through at least a majority of the semiconductor substrate at an angle substantially perpendicular with the crystal plane of the non-cubic crystalline lattice of the semiconductor substrate

aligning a second saw blade substantially perpendicularly with the semiconductor substrate; and

cutting entirely through the semiconductor substrate using the second saw blade.

2. The method of claim 1 , wherein the non-cubic crystalline lattice is hexagonal.

3. The method of claim 1 , wherein the crystal plane is angled at four degrees from a largest planar surface of the semiconductor substrate.

4. The method of claim 1 , wherein the first saw blade is aligned by tilting relative to the semiconductor substrate.

5. The method of claim 1 , wherein the first saw blade is aligned by tilting the semiconductor substrate relative to the first saw blade.

6. The method of claim 1 , wherein cutting through at least the majority of the semiconductor substrate further comprises cutting through 95% of the semiconductor substrate.

7. The method of claim 1 , wherein cutting through at least the majority of the semiconductor substrate further comprises cutting through 99% of the semiconductor substrate.

8. A method for cutting a silicon carbide semiconductor substrate comprising:

aligning a first saw blade substantially perpendicularly with an off angle of a crystal lattice of a silicon carbide semiconductor substrate;

cutting through at least a majority of the silicon carbide semiconductor substrate with the first saw blade at a substantially perpendicular angle;

aligning a second saw blade substantially perpendicularly with the silicon carbide semiconductor substrate; and

cutting entirely through the silicon carbide semiconductor substrate using the second saw blade.

9. The method of claim 8 , wherein cutting through at least the majority of the silicon carbide semiconductor substrate further comprises cutting through 95% of the silicon carbide semiconductor substrate.

10. The method of claim 8 , wherein the crystal lattice is angled at four degrees relative to a largest planar surface of the silicon carbide semiconductor substrate.

11. The method of claim 8 , wherein the first saw blade is aligned by tilting relative to the silicon carbide semiconductor substrate.

12. The method of claim 8 , wherein the first saw blade is aligned by tilting the silicon carbide semiconductor substrate relative to the first saw blade.

13. A method for singulating a silicon carbide semiconductor substrate comprising:

aligning a first saw blade substantially parallel with a c-axis of a silicon carbide semiconductor substrate;

cutting through at least a majority of the silicon carbide semiconductor substrate at an angle substantially parallel with the c-axis of the silicon carbide semiconductor substrate;

aligning a second saw blade substantially perpendicularly with the silicon carbide semiconductor substrate; and

singulating the silicon carbide semiconductor substrate into a plurality of semiconductor die by cutting entirely through the silicon carbide semiconductor substrate using the second saw blade.

14. The method of claim 13 , further comprising tilting the first saw blade relative to the silicon carbide semiconductor substrate from a first position to a second position and cutting the silicon carbide semiconductor substrate in a first direction.

15. The method of claim 14 , further comprising tilting the first saw blade back to the first position.

16. The method of claim 14 , further comprising tilting the silicon carbide semiconductor substrate relative to the first saw blade and cutting the silicon carbide substrate in a second position.

17. The method of claim 13 , wherein the first saw blade and the second saw blade comprise diamond.

18. The method of claim 13 , wherein the c-axis is angled at four degrees relative to a largest planar surface of the silicon carbide semiconductor substrate.

19. The method of claim 13 , wherein a first sidewall and a second sidewall of each semiconductor die of the plurality of semiconductor die are each angled relative to a largest planar surface of each semiconductor die.

20. The method of claim 19 , wherein a third sidewall and a fourth sidewall of each semiconductor die of the plurality of semiconductor die are each substantially perpendicular to the largest planar surface of each semiconductor die.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 053613, FRAME 0621 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0942 →
SECURITY INTEREST Recorded Jul 13, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; GTAT CORPORATION
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064271/0971 →
SECURITY INTEREST Recorded Aug 27, 2020
From: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 053613/0621 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2020
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 052585/0569 →
Continuity (3)
Continuation 16674780 · Nov 5, 2019
Continuation In Part 15964496 · Apr 27, 2018
Related Publication 20200266106A1 · Aug 20, 2020