IP Library Granted Patent US 11,257,847
Granted Patent B2
US 11,257,847 · App. 16/923,395 · Granted Feb 22, 2022

Display device including transistor and manufacturing method thereof

Inventors: Junichiro Sakata (Atsugi, JP); Toshinari Sasaki (Atsugi, JP); Miyuki Hosoba (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1225H01L21/02554H01L21/02565H01L21/02631H01L27/124H01L27/127H01L27/1218H01L29/24H01L29/66969H01L29/7869H01L29/78633H01L29/78645H01L29/78648H01L29/78654H01L29/78696
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Quick Facts
Patent No.
US 11,257,847
App. No.
16/923,395
Granted
Feb 22, 2022
Kind
B2
Abstract

An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Claims (35)

1. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region of a transistor;

a first gate electrode below the oxide semiconductor layer;

a second gate electrode over the oxide semiconductor layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer; and

an insulating layer between the first gate electrode and each of the source electrode and the drain electrode,

wherein the first gate electrode comprises a region overlapping with a contact hole in the insulating layer,

wherein the region of the first gate electrode is in contact with one of the source electrode and the drain electrode, and

wherein in a plan view of the semiconductor device, the contact hole does not overlap with the oxide semiconductor layer and is located in a region extending in a channel length direction of the transistor from a periphery of the oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein in the channel length direction of the transistor, the second gate electrode is smaller than the oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein in the channel length direction of the transistor, the first gate electrode is larger than the oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode are over the oxide semiconductor layer.

5. The semiconductor device according to claim 1 , further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

6. The semiconductor device according to claim 5 , wherein the pixel electrode comprises indium tin oxide.

7. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a crystal region.

9. A semiconductor device comprising:

an oxide semiconductor layer comprising a channel formation region of a transistor;

a first gate electrode below the oxide semiconductor layer;

a second gate electrode over the oxide semiconductor layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer; and

an insulating layer between the first gate electrode and each of the source electrode and the drain electrode,

wherein the first gate electrode comprises a region overlapping with a contact hole in the insulating layer,

wherein the region of the first gate electrode is in contact with one of the source electrode and the drain electrode,

wherein in a plan view of the semiconductor device, the contact hole does not overlap with the oxide semiconductor layer and is located in a region extending in a channel length direction of the transistor from an outer edge of the oxide semiconductor layer, and

wherein an end portion of the oxide semiconductor layer comprises a region which is not in contact with the source electrode or the drain electrode.

10. The semiconductor device according to claim 9 , wherein in the channel length direction of the transistor, the second gate electrode is smaller than the oxide semiconductor layer.

11. The semiconductor device according to claim 9 , wherein in the channel length direction of the transistor, the first gate electrode is larger than the oxide semiconductor layer.

12. The semiconductor device according to claim 9 , wherein the source electrode and the drain electrode are over the oxide semiconductor layer.

13. The semiconductor device according to claim 9 , further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

14. The semiconductor device according to claim 13 , wherein the pixel electrode comprises indium tin oxide.

15. The semiconductor device according to claim 9 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

16. The semiconductor device according to claim 9 , wherein the oxide semiconductor layer comprises a crystal region.

Priority Claims (1)
JP 2009-159052 · Jul 3, 2009 · national
Continuity (8)
Continuation 16270079 · Feb 7, 2019
Continuation 15827318 · Nov 30, 2017
Continuation 15096663 · Apr 12, 2016
Continuation 14804508 · Jul 21, 2015
Continuation 14228663 · Mar 28, 2014
Continuation 13632709 · Oct 1, 2012
Continuation 12828464 · Jul 1, 2010
Related Publication 20200343276A1 · Oct 29, 2020
Cited By (3)
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