Granted Patent B2

US 12,266,725 · App. 16/923,587 · Granted Apr 1, 2025

Inventors: Umesh Mishra (Montecito, CA); Davide Bisi (Goleta, CA); Geetak Gupta (Goleta, CA); Carl Joseph Neufeld (Goleta, CA); Brian L. Swenson (Santa Barbara, CA); Rakesh K. Lal (Isla Vista, CA)

Assignee: Transphorm Technology, Inc.

H01L29/7788H01L29/0692H01L29/1037H01L29/205H01L29/66462H01L29/7783H01L29/2003

Abstract

Claims (18)

1. A III-N device, comprising:

a III-N material structure comprising a III-N channel layer over a III-N barrier layer, a p-type III-N layer over and directly contacting the III-N channel layer, and a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer;

an n-type III-N layer over and directly contacting the p-type III-N layer,

a source electrode, a gate electrode, and a drain electrode each on a same side of the III-N material structure;

a gate insulator layer separating the gate electrode from the p-type III-N layer and the III-N channel layer; wherein

the source electrode directly contacts the n-type III-N layer and is electrically connected to the p-type III-N layer;

the drain electrode is electrically connected to the 2DEG channel;

a portion of the III-N channel layer separates the gate insulator layer from the III-N barrier layer;

the p-type III-N layer is over the III-N channel layer in a source side access region of the device and does not extend past the gate electrode; and

the 2DEG channel extends continuously through the III-N channel layer from below the source electrode to the drain electrode and the source electrode is electrically isolated from a portion of the 2DEG channel below the source electrode when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage of the device.

2. The device of claim 1 , wherein the III-N material structure is grown in an N-polar orientation.

3. The device of claim 1 , further comprising a first Al x Ga 1−x N layer between the p-type III-N layer and the n-type III-N layer, wherein x is between 0.5 and 1, and a thickness of the Al x Ga 1−x N layer is between 0.5 nm and 5 nm.

4. The device of claim 3 , further comprising a second Al x Ga 1−x N layer between the p-type III-N layer and the III-N channel layer, wherein x is between 0.5 and 1, and a thickness of the Al x Ga 1−x N layer is between 0.5 nm and 5 nm.

5. The device of claim 1 , wherein the gate insulator layer and the gate electrode are formed over a vertical or slanted sidewall of the p-type III-N layer in a gate region of the device, the gate electrode further comprising a first portion extending towards the source electrode and a second portion extending towards the drain electrode.

6. The device of claim 5 , wherein an angle between the vertical or slanted sidewall of the p-type III-N layer and a top surface of the III-N material structure opposite is between 20° and 80°.

7. The device of claim 1 , wherein the source electrode is directly contacting and electrically connected to the p-type III-N layer.

8. The device of claim 1 , wherein when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage of the device, the 2DEG channel is fully depleted in a source-side region adjacent the source electrode.

9. The device of claim 1 , wherein when the gate electrode is biased relative to the source electrode at a voltage that is above a threshold voltage and a positive voltage is applied to the drain electrode, electrons flow from the source towards the drain through the n-type III-N layer.

Assignments (3)

Continuity (3)

References Cited (227)