IP Library Granted Patent US 11,322,498
Granted Patent B2
US 11,322,498 · App. 16/944,289 · Granted May 3, 2022

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1052G11C11/405G11C16/0433H01L27/105H01L27/115H01L27/1156H01L27/11551H01L27/11803H01L27/124H01L27/1207H01L27/1225H01L27/1255H01L29/16H01L29/24H01L29/247H01L29/7869H01L29/78693H01L29/78696G11C2211/4016H01L21/8221H01L27/0688H01L27/108H01L29/7833
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Quick Facts
Patent No.
US 11,322,498
App. No.
16/944,289
Granted
May 3, 2022
Kind
B2
Abstract

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Claims (58)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a first insulating layer over a channel formation region of the first transistor and a channel formation region of the third transistor; and

a second insulating layer over the first insulating layer,

wherein a channel formation region of the second transistor is over the second insulating layer,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a semiconductor material of a semiconductor layer of the first transistor and a semiconductor material of a semiconductor layer of the third transistor comprise silicon,

wherein a semiconductor material of a semiconductor layer of the second transistor comprises an oxide semiconductor comprising In, Ga, and Zn,

wherein a conductive layer having a region in contact with a top surface of the semiconductor layer of the second transistor is electrically connected to the gate of the first transistor through an opening provided in the first insulating layer and the second insulating layer,

wherein a gate of the second transistor is provided under the channel formation region of the second transistor,

wherein, in a plan view, a conductive layer having a region functioning as the gate of the second transistor extends in a first direction,

wherein the gate of the first transistor is provided over the channel formation region of the first transistor, and

wherein, in the plan view, a conductive layer having a region functioning as the gate of the first transistor extends in a second direction intersecting with the first direction.

2. The display device according to claim 1 , wherein any one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon nitride.

3. The display device according to claim 1 , further comprising a first wiring and a second wiring.

4. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a capacitor;

a first insulating layer; and

a second insulating layer,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a first electrode of the capacitor is electrically connected to the one of a source and a drain of the second transistor and to the gate of the first transistor,

wherein a second electrode of the capacitor is electrically connected to the other of the source and drain of the first transistor,

wherein a semiconductor material of a semiconductor layer of the first transistor and a semiconductor material of a semiconductor layer of the third transistor comprise silicon,

wherein a semiconductor material of a semiconductor layer of the second transistor comprises an oxide semiconductor comprising In, Ga, and Zn,

wherein a conductive layer having a region in contact with a top surface of the semiconductor layer of the second transistor is electrically connected to the gate of the first transistor through an opening provided in the first insulating layer and the second insulating layer,

wherein a gate of the second transistor is provided under a channel formation region of the second transistor,

wherein, in a plan view, a conductive layer having a region functioning as the gate of the second transistor extends in a first direction,

wherein the gate of the first transistor is provided over a channel formation region of the first transistor, and

wherein, in the plan view, a conductive layer having a region functioning as the gate of the first transistor extends in a second direction intersecting with the first direction.

5. The display device according to claim 4 , wherein any one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon nitride.

6. The display device according to claim 4 , further comprising a first wiring and a second wiring.

7. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a capacitor;

a first insulating layer; and

a second insulating layer over the first insulating layer,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,

wherein a first electrode of the capacitor is electrically connected to the one of a source and a drain of the second transistor and to the gate of the first transistor,

wherein a second electrode of the capacitor is electrically connected to the other of the source and drain of the first transistor,

wherein a semiconductor material of a semiconductor layer of the first transistor and a semiconductor material of a semiconductor layer of the third transistor comprise silicon,

wherein a semiconductor material of a semiconductor layer of the second transistor comprises an oxide semiconductor,

wherein a conductive layer having a region in contact with a top surface of the semiconductor layer of the second transistor is electrically connected to the gate of the first transistor,

wherein a gate of the second transistor is provided under a channel formation region of the second transistor,

wherein, in a plan view, a conductive layer having a region functioning as the gate of the second transistor extends in a first direction,

wherein the gate of the first transistor is provided over a channel formation region of the first transistor, and

wherein, in the plan view, a conductive layer having a region functioning as the gate of the first transistor extends in a second direction intersecting with the first direction.

8. The display device according to claim 7 , wherein any one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon nitride.

9. The display device according to claim 7 , further comprising a first wiring and a second wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2020
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; KATO, KIYOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 053367/0487 →
Priority Claims (1)
JP 2009-251261 · Oct 30, 2009 · national
Continuity (7)
Continuation 16558386 · Sep 3, 2019
Continuation 15615873 · Jun 7, 2017
Continuation 15175190 · Jun 7, 2016
Continuation 14804478 · Jul 21, 2015
Continuation 14336107 · Jul 21, 2014
Division 12914672 · Oct 28, 2010
Related Publication 20200365592A1 · Nov 19, 2020
Cited By (7)
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