Semiconductor structure having sets of III-V compound layers and method of forming

1. A semiconductor structure comprising:

a substrate;

a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant type of adjacent III-V layers of the plurality of III-V layers;

an active layer over the buffer layer, wherein the active layer consists of a single layer; and

a dielectric layer over the active layer, wherein the dielectric layer is continuous over an entirety of the active layer.

2. The semiconductor structure of claim 1 , further comprising a channel layer between the buffer layer and the active layer.

3. The semiconductor structure of claim 2 , further comprising a source electrode directly contacting the channel layer.

4. The semiconductor structure of claim 1 , wherein at least one of the plurality of III-V layers comprises GaN.

5. The semiconductor structure of claim 1 , further comprising a nucleation layer between the substrate and the buffer layer.

6. The semiconductor structure of claim 5 , wherein the nucleation layer comprises AN.

7. The semiconductor structure of claim 5 , wherein the nucleation layer is configured to reduce lattice mismatch between the substrate and the buffer layer.

8. The semiconductor structure of claim 1 , wherein the buffer layer directly contacts the substrate.

9. A method of forming a semiconductor structure, the method comprising:

forming a nucleation layer over a substrate;

growing a buffer layer over the nucleation layer, wherein growing the buffer layer comprises growing a plurality of pairs of layers, each pair of layers of the plurality of pairs of layers includes a lower III-V compound layer and an upper III-V compound layer, the lower III-V compound layer is undoped or has a first doping type, and the upper III-V compound layer has a second doping type opposite the first doping type;

growing a channel layer over the buffer layer;

forming an active layer over the channel layer, wherein the channel layer extends beyond the active layer in a direction parallel to a top surface of the substrate; and

depositing a dielectric layer over the active layer.

10. The method of claim 9 , further comprising growing a transition layer over the nucleation layer, wherein the transition layer is between the nucleation layer and the buffer layer.

11. The method of claim 10 , wherein the growing the transition layer comprises growing a graded AlGaN layer.

12. The method of claim 9 , wherein forming the nucleation layer comprises depositing AN.

13. The method of claim 9 , further comprising forming a plurality of electrodes, wherein the plurality of electrodes comprises a plurality of source/drain (S/D) electrodes and a gate electrode.

14. The method of claim 13 , wherein the forming the plurality of electrodes comprises forming each of the S/D electrodes in direct contact with the channel layer.

15. The method of claim 13 , wherein forming the gate structure comprises forming the gate electrode closer to a first S/D electrode of the plurality of S/D electrodes than to a second S/D electrode of the plurality of S/D electrodes.

16. A semiconductor structure, comprising:

a substrate;

a first GaN layer over the substrate, the first GaN layer having P-type doping;

a second GaN layer over the first GaN layer, wherein the second GaN layer is undoped;

a third GaN layer over the second GaN layer, wherein the third GaN layer is P-type doped;

a fourth GaN layer over the third GaN layer, the fourth GaN layer being undoped;

a channel layer over the fourth GaN layer; and

an active layer over the channel layer, wherein the channel layer extends beyond the active layer in a direction parallel to a top surface of the substrate.

17. The semiconductor structure of claim 16 , further comprising a dielectric layer directly contacting the active layer.

18. The semiconductor structure of claim 16 , further comprising a nucleation layer between the first GaN layer and the substrate.

19. The semiconductor structure of claim 16 , further comprising a two-dimensional electron gas (2-DEG) in the channel layer.

20. The semiconductor structure of claim 16 , wherein the first GaN layer directly contacts the substrate.