IP Library Granted Patent US 11,710,691
Granted Patent B2
US 11,710,691 · App. 17/082,512 · Granted Jul 25, 2023

Semiconductor device and method of forming micro interconnect structures

Inventors: Francis J. Carney (Mesa, AZ); Jefferson W. Hall (Chandler, AZ); Michael J. Seddon (Gilbert, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49827H01L21/02035H01L21/288H01L21/304H01L21/308H01L21/3065H01L21/3083H01L21/486H01L21/4825H01L21/4853H01L21/565H01L21/67069H01L21/6835H01L21/76877H01L21/76898H01L21/78H01L22/12H01L22/26H01L23/3107H01L23/3114H01L23/481H01L23/4822H01L23/4951H01L23/49503H01L23/49541H01L23/49562H01L23/49575H01L23/49811H01L23/49838H01L23/49866H01L23/544H01L23/562H01L24/00H01L24/05H01L25/0655H01L25/0657H01L25/50H01L27/0207H01L27/088H01L27/14H01L27/14683H01L29/0847H02M3/158H01L23/147H01L23/15H01L23/3677H01L23/49816H01L27/14625H01L27/14685H01L2221/68327H01L2223/5446H01L2223/54426H01L2224/0401H01L2224/04042H01L2224/05083H01L2224/05084H01L2224/05124H01L2224/05139H01L2224/05144H01L2224/05147H01L2224/05155H01L2224/05164H01L2224/05166H01L2224/05171H01L2224/05172H01L2224/05184H01L2224/13025H01L2224/13111H01L2224/13116H01L2225/06555H01L2225/06593H01L2225/06596H01L2924/13055H01L2924/13091H01L2924/3511
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Quick Facts
Patent No.
US 11,710,691
App. No.
17/082,512
Granted
Jul 25, 2023
Kind
B2
Abstract

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Claims (34)

1. A semiconductor device, comprising:

a first substrate comprising an active surface and one or more side surfaces substantially perpendicular to the active surface;

a plurality of recesses formed in the one or more side surfaces of the first substrate;

one or more second substrates comprising an active surface and two or more side surfaces substantially perpendicular to the active surface;

extensions comprised on the two or more side surfaces of the one or more second substrates;

a first conductive layer formed on the active surface and the one or more side surfaces of the first substrate;

a second conductive layer on the active surface and the two or more side surfaces of the one or more second substrates; and

an interconnect formed over the first conductive layer of the first substrate and the second conductive layer of the one or more second substrates;

wherein the one or more second substrates are electrically and mechanically coupled with the first substrate at the extensions; and

wherein the first substrate includes a polygonal shape.

2. The device of claim 1 , wherein the interconnect includes a conductive material formed over a junction between the first conductive layer of the first substrate and the second conductive layer of the one or more second substrates.

3. The device of claim 1 , wherein the first conductive layer of the first substrate and the second conductive layer of the one or more second substrates include a conductive epoxy or anisotropic conductive film.

4. The device of claim 1 , wherein the first substrate has more than four side surfaces.

5. The device of claim 1 , wherein an extension of the extensions has an angled profile and a recess of the plurality of recesses has an angled profile.

6. The device of claim 1 , wherein the one or more side surfaces of the first substrate and the two or more side surfaces of the one or more second substrates are angled.

7. The device of claim 1 , further including a third substrate comprising an active surface and a side surface substantially perpendicular to the active surface and comprising a third conductive layer comprised over a portion of the active surface and the side surface.

8. The device of claim 1 , wherein the first conductive layer and the second conductive layer comprise one of Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and any combination thereof.

9. A semiconductor device, comprising:

a first substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface;

a plurality of recesses formed in the one or more side surfaces of the first substrate;

a second substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface;

one or more extensions comprised on the one or more side surfaces of the second substrate;

a first conductive layer formed on the one or more side surfaces of the first substrate;

a second conductive layer on the one or more side surfaces of the second substrate; and

an interconnect coupled to the first conductive layer of the first substrate and to the second conductive layer of the second substrate;

wherein the second substrate is electrically and mechanically coupled with the first substrate at the one or more extensions; and

wherein the one or more extensions each have an angled profile and the plurality of recesses each have an angled profile.

10. The device of claim 9 , wherein the interconnect includes a conductive material formed over a junction between the first conductive layer of the first substrate and the second conductive layer of the second substrate.

11. The device of claim 9 , wherein the first conductive layer of the first substrate and the second conductive layer of the second substrate includes a conductive epoxy or anisotropic conductive film.

12. The device of claim 9 , wherein the first substrate has more than four side surfaces.

13. The device of claim 9 , wherein the first substrate includes a polygonal shape.

14. The device of claim 9 , wherein the one or more side surfaces of the first substrate and of the second substrate are angled.

15. The device of claim 9 , further including a third substrate comprising a first surface and one or more side surfaces substantially perpendicular to the first surface and comprising a third conductive layer comprised over a portion of the first surface and the one or more side surfaces.

16. The device of claim 9 , wherein the first conductive layer and the second conductive layer comprise one of Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and any combination thereof.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 055315, FRAME 0350 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0881 →
SECURITY INTEREST Recorded Feb 17, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 055315/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2020
From: CARNEY, FRANCIS J.; HALL, JEFFERSON W.; SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 054196/0407 →
Continuity (4)
Division 16131462 · Sep 14, 2018
Continuation 15218974 · Jul 25, 2016
Provisional Application 62219666 · Sep 17, 2015
Related Publication 20210043553A1 · Feb 11, 2021
Cited By (1)
US 12,230,559