IP Library Granted Patent US 11,302,812
Granted Patent B2
US 11,302,812 · App. 17/087,218 · Granted Apr 12, 2022

Semiconductor device with fin and related methods

Inventors: Pierre Morin (Kessel-Lo, BE); Nicolas Loubet (Guilderland, NY)
Assignee: STMICROELECTRONICS, INC.
H01L29/7848H01L27/0886H01L29/165H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,302,812
App. No.
17/087,218
Granted
Apr 12, 2022
Kind
B2
Abstract

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Claims (34)

1. A method, comprising:

forming a semiconductor fin over a dielectric layer that is over a top surface of a substrate, the semiconductor fin extending in a first direction;

forming a plurality of gate structures over the semiconductor fin, the plurality of gate structures extending in a second direction that is canted with respect to the first direction;

forming recesses on opposite sides of the plurality of gate structures, the recesses exposing the top surface of the substrate; and

epitaxially growing a semiconductor material in the recesses.

2. The method of claim 1 wherein the epitaxially growing the semiconductor material in the recesses comprises epitaxially growing the semiconductor material from top surface of the substrate and sidewall surfaces of remaining portions of the semiconductor fin.

3. The method of claim 1 wherein the forming the recesses comprises removing portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures.

4. The method of claim 3 wherein the removing portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures comprises etching the portions of the semiconductor fin and the dielectric layer on the opposite sides of the plurality of gate structures.

5. The method of claim 1 wherein the epitaxially growing the semiconductor material in the recesses comprises epitaxially growing silicon germanium in the recesses.

6. The method of claim 1 wherein the recesses expose sidewalls of remaining portions of the semiconductor fin and remaining portions of the dielectric layer.

7. A method, comprising:

forming a fin-shaped semiconductor structure over a substrate, the fin-shaped semiconductor structure oriented along a first direction;

forming a gate structure that interfaces the fin-shaped semiconductor structure at two or more surfaces of the fin-shaped semiconductor structure; and

forming a source or drain structure on a side of the gate structure, the source or drain structure interfacing with an edge surface of the fin-shaped semiconductor structure, the edge surface being at an oblique angle to the first direction.

8. The method of claim 7 wherein the forming the source or drain structure includes:

forming a recess in the fin-shaped semiconductor structure, the recess having a sidewall surface at the oblique angle to the first direction; and

epitaxially growing a semiconductor layer in the recess.

9. The method of claim 8 wherein the semiconductor layer is silicon germanium.

10. The method of claim 9 wherein the fin-shaped semiconductor structure is silicon.

11. The method of claim 7 wherein the oblique angle is in a range from 22.5 degrees to 67.5 degrees.

12. The method of claim 7 wherein the oblique angle is in a range from 40 degrees to 50 degrees.

13. The method of claim 8 wherein the forming the recess forms the recess through the fin-shaped semiconductor structure and exposes the substrate through the recess.

14. The method of claim 7 , comprising forming a dielectric layer over the substrate,

wherein the fin-shaped semiconductor structure is formed over the dielectric layer.

15. A method, comprising:

forming a plurality of semiconductor fin structures over a substrate, the plurality of semiconductor fin structures each oriented in a first direction;

forming a plurality of gate structures each overlapping the plurality of semiconductor fin structures, the plurality of gate structures each oriented along a second direction that is at an oblique angle to the first direction;

forming recesses in the plurality of semiconductor fin structures between the plurality of gate structures; and

forming source or drain structures in the recesses, the source or drain structures extending in the second direction.

16. The method of claim 15 wherein the oblique angle is in a range from 22.5 degrees to 67.5 degrees.

17. The method of claim 15 wherein the substrate is silicon.

18. The method of claim 15 wherein the forming the source or drain structures includes growing an epitaxial semiconductor layer in the recesses.

19. The method of claim 15 wherein the source or drain structures each contacts a respective one of the plurality of semiconductor fin structures at a surface along the second direction.

20. The method of claim 15 wherein the recesses are formed to reach the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2022
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061915/0364 →
Continuity (7)
Division 16680222 · Nov 11, 2019
Continuation 16212632 · Dec 6, 2018
Continuation 15723152 · Oct 2, 2017
Continuation 15255862 · Sep 2, 2016
Continuation 14663843 · Mar 20, 2015
Provisional Application 61972527 · Mar 31, 2014
Related Publication 20210050449A1 · Feb 18, 2021