Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling
Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.
1. An integrated circuit package, comprising:
a package substrate having a first face and an opposing second face, and wherein the package substrate includes a plurality of layers;
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers at the first face of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um, and wherein a diameter of an individual pillar of the plurality of pillars is between 2 um and 20 um; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via; and
a first die, wherein the first die is electrically coupled to an individual pillar of the plurality of pillars on the high-density interconnect layer.
2. The integrated circuit package of claim 1 , wherein a diameter of the via is between 2 um and 10 um.
3. The integrated circuit package of claim 1 , further comprising:
a cavity formed on the package substrate.
4. The integrated circuit package of claim 3 , further comprising:
a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate.
5. The integrated circuit package of claim 4 , further comprising:
a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die.
6. The integrated circuit package of claim 1 , wherein an I/O of an individual layer of the plurality of layers of the package substrate that is not the high-density interconnect layer is between 15 and 60 I/O/mm/layer.
7. The integrated circuit package of claim 1 , wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um.
8. A computing device, comprising:
a circuit board; and
an integrated circuit package coupled to the circuit board, wherein the integrated circuit package comprises:
a package substrate having a first face and an opposing second face and wherein the package substrate includes a plurality of layers;
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate and is at the first face of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via, wherein a diameter of the via is between 2 um and 10 um; and
a first die, wherein the first die is electrically coupled to the package substrate via one or more of the plurality of pillars on the high-density interconnect layer.
9. The computing device of claim 8 , wherein a diameter of an individual pillar of the plurality of pillars is between 2 um and 20 um.
10. The computing device of claim 8 , wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um.
11. The computing device of claim 8 , further comprising:
a cavity formed on the package substrate.
12. The computing device of claim 11 , further comprising:
a second die in the cavity formed on the package substrate, wherein the second die is conductively connected to the package substrate.
13. The computing device of claim 12 , further comprising:
a third die in the cavity formed on the package substrate, wherein the third die is conductively connected to the second die.
14. An integrated circuit assembly, comprising:
a package substrate having a first face and an opposing second face, and wherein the package substrate includes a plurality of layers; and
a high-density interconnect layer having a first side and an opposing second side, wherein the high-density interconnect layer is an individual layer of the plurality of layers of the package substrate at the first face of the package substrate, wherein an input/output (I/O) of the high-density interconnect layer is between 100 and 1000 I/O/mm/layer, and wherein the high-density interconnect layer includes:
a plurality of pillars formed on the first side of the high-density interconnect layer, wherein a bump pitch of the plurality of pillars is between 10 um and 80 um, and wherein a diameter of an individual pillar of the plurality of pillars is between 2 um and 20 um; and
a via formed on the second side of the high-density interconnect layer, wherein a next individual layer of the plurality of layers of the package substrate is electrically coupled to the via.
15. The integrated circuit assembly of claim 14 , wherein an I/O of an individual layer of the plurality of layers of the package substrate that is not the high-density interconnect layer is between 15 and 60 I/O/mm/layer.
16. The integrated circuit assembly of claim 14 , wherein a bump pitch of the second face of the package substrate is between 200 um and 1000 um.
17. The integrated circuit assembly of claim 14 , wherein a diameter of the via is between 2 um and 10 um.
18. The integrated circuit assembly of claim 14 , wherein the high-density interconnect layer further includes a pad formed on the second side of the high-density interconnect layer and the pad has a pad size between 1 um and 24 um.