IP Library Granted Patent US 11,805,642
Granted Patent B2
US 11,805,642 · App. 17/149,029 · Granted Oct 31, 2023

Semiconductor device

Inventor: Wataru Sakamoto (Yokkaichi, JP)
Assignee: Kioxia Corporation
H10B41/27H01L29/1037H01L29/40114H01L29/40117H10B41/10H10B41/35H10B43/10H10B43/27H10B43/35
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Quick Facts
Patent No.
US 11,805,642
App. No.
17/149,029
Granted
Oct 31, 2023
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

Claims (109)

1. A method for manufacturing a semiconductor device, comprising:

forming a first electrode layer above a substrate;

forming a first insulator on the first electrode layer;

forming a second electrode layer on the first insulator;

forming a hole through the second electrode layer, the first insulator, and the first electrode layer, the hole extending in a first direction;

recessing the first electrode layer and the second electrode layer via the hole, a first space being formed by the recessing the first electrode layer, and a second space being formed by the recessing the second electrode layer; and

forming a first charge storage portion in the first space and a second charge storage portion in the second space, wherein

a first diameter of a first part of the hole located in the first charge storage portion is smaller than a second diameter of a second part of the hole located in the second charge storage portion, and

a first thickness of the first charge storage portion is thinner than a second thickness of the second charge storage portion in a second direction intersecting the first direction.

2. The method according to claim 1 , further comprising:

forming a third electrode layer on the first insulator; and

forming a second insulator on the third electrode layer, wherein

the second electrode layer is formed on the second insulator,

in the forming the hole, the hole passes through the second insulator and the third electrode layer,

in the recessing the first electrode layer and the second electrode layer, the third electrode layer is recessed, and a third space is formed by the recessing the third electrode layer,

in the forming the first charge storage portion and the second charge storage portion, a third charge storage portion is formed in the third space,

a third diameter of a third part of the hole located in the third charge storage portion is larger than the first diameter and is smaller than the second diameter, and

a third thickness of the third charge storage portion is thicker than the first thickness and is thinner than the second thickness in the second direction.

3. The method according to claim 1 , wherein the recessing the first electrode layer and the second electrode layer includes:

forming a first member at a lower part of the hole, the first part of the hole being located in the lower part, and the second part of the hole being located above the lower part,

recessing the second electrode layer via the hole,

removing the first member, and

recessing the first electrode layer via the hole.

4. The method according to claim 1 , wherein

the first electrode layer and the second electrode layer include silicon and impurity, and

an impurity concentration of the second electrode layer is higher than an impurity concentration of the first electrode layer.

5. The method according to claim 1 , wherein

the first electrode layer and the second electrode layer include a metal.

6. The method according to claim 1 , wherein the hole has a tapered shape.

7. The method according to claim 1 , further comprising:

forming a first block insulating film on an inner wall of the first space and a second block insulating film on an inner wall of the second space, before the forming the first charge storage portion and the second charge storage portion;

forming a tunnel insulating film on an inner surface of the hole, after the forming the first charge storage portion and the second charge storage portion; and

forming a semiconductor body on an inner surface of the tunnel insulating film.

8. The method according to claim 7 , further comprising:

forming a separating portion in the second electrode layer, the first insulator and the first electrode layer, the separating portion extending in the first direction; and

forming a source layer extending in the first direction in the separating portion, the source layer being electrically connected to a bottom end of the semiconductor body.

9. A method for manufacturing a semiconductor device, comprising:

forming a first electrode layer above a substrate;

forming a first insulator on the first electrode layer;

forming a second electrode layer on the first insulator;

forming a first hole through the second electrode layer, the first insulator and the first electrode layer, the first hole extending in a first direction;

recessing the first electrode layer and the second electrode layer via the first hole, a first space being formed by the recessing the first electrode layer, and a second space being formed by the recessing the second electrode layer;

forming a first charge storage portion in the first space and a second charge storage portion in the second space;

forming a third electrode layer above the second electrode layer;

forming a second insulator on the third electrode layer;

forming a fourth electrode layer on the second insulator;

forming a second hole through the fourth electrode layer, the second insulator and the third electrode layer, the second hole extending in the first direction;

recessing the third electrode layer and the fourth electrode layer via the second hole, a third space being formed by the recessing the third electrode layer, and a fourth space being formed by the recessing the fourth electrode layer; and

forming a third charge storage portion in the third space and a fourth charge storage portion in the fourth space, wherein

a first diameter of a first part of the first hole located in the first charge storage portion is smaller than a second diameter of a second part of the first hole located in the second charge storage portion,

a third diameter of a third part of the second hole located in the third charge storage portion is smaller than a fourth diameter of a fourth part of the second hole located in the fourth charge storage portion,

a first thickness of the first charge storage portion is thinner than a second thickness of the second charge storage portion in a second direction intersecting the first direction, and

a third thickness of the third charge storage portion is thinner than a fourth thickness of the fourth charge storage portion in the second direction.

10. The method according to claim 9 , further comprising:

forming a first member in the first hole, after the forming the first charge storage portion and the second charge storage portion, and before the forming the third electrode layer; and

removing the first member, after the forming the third charge storage portion and the fourth charge storage portion.

11. The method according to claim 9 , wherein

the third diameter is smaller than the second diameter.

12. The method according to claim 9 , wherein the recessing the first electrode layer and the second electrode layer includes:

forming a second member at a lower part of the first hole, the first part of the first hole being located in the lower part, and the second part of the first hole being located above the lower part,

recessing the second electrode layer via the first hole,

removing the second member, and

recessing the first electrode layer via the first hole.

13. The method according to claim 9 , wherein the recessing the third electrode layer and the fourth electrode layer includes:

forming a second member at a lower part of the second hole, the third part of the second hole being located in the lower part, and the forth part of the second hole being located above the lower part,

recessing the fourth electrode layer via the second hole,

removing the second member, and

recessing the third electrode layer via the second hole.

14. The method according to claim 9 , wherein

the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer include silicon and impurity,

an impurity concentration of the second electrode layer is higher than an impurity concentration of the first electrode layer, and

an impurity concentration of the fourth electrode layer is higher than an impurity concentration of the third electrode layer.

15. The method according to claim 9 , wherein

the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer include a metal.

16. The method according to claim 9 , wherein

the first hole has a tapered shape, and

the second hole has a tapered shape.

17. The method according to claim 9 , further comprising:

forming a first block insulating film on an inner wall of the first space and a second block insulating film on an inner wall of the second space, before the forming the first charge storage portion and the second charge storage portion;

forming a third block insulating film on an inner wall of the third space and a fourth block insulating film on an inner wall of the fourth space, before the forming the third charge storage portion and the fourth charge storage portion;

forming a tunnel insulating film on an inner surface of the first hole and an inner surface of the second hole; and

forming a semiconductor body on an inner surface of the tunnel insulating film.

18. The method according to claim 17 , further comprising:

forming an insulating body on an inner surface of the semiconductor body.

19. The method according to claim 17 , further comprising:

forming a separating portion in the fourth electrode layer, the second insulator, the third electrode layer, the second electrode layer, the first insulator and the first electrode layer, the separating portion extending in the first direction; and

forming a source layer extending in the first direction in the separating portion, the source layer being electrically connected to a bottom end of the semiconductor body.

20. A method for manufacturing a semiconductor device, comprising:

forming a first layer above a substrate;

forming an insulator on the first layer;

forming a second layer on the insulator;

forming a hole through the second layer, the insulator and the first layer, the hole extending in a first direction;

recessing the first layer and the second layer via the hole, a first space being formed by the recessing the first layer, and a second space being formed by the recessing the second layer;

forming a first charge storage portion in the first space and a second charge storage portion in the second space;

forming a tunnel insulating film on an inner surface of the hole;

forming a semiconductor body on an inner surface of the tunnel insulating film;

forming a separating portion in the second layer, the insulator and the first layer, the separating portion extending in the first direction;

recessing the first layer and the second layer via the separating portion, a third space being formed by the recessing the first layer via the separating portion, and a fourth space being formed by the recessing the second layer via the separating portion;

forming a first block insulating film on an inner wall of the third space and a second block insulating film on an inner wall of the fourth space; and

forming a first electrode layer in the third space and a second electrode layer in the fourth space, wherein

a first diameter of a first part of the hole located in the first charge storage portion is smaller than a second diameter of a second part of the hole located in the second charge storage portion, and

a first thickness of the first charge storage portion is thinner than a second thickness of the second charge storage portion in a second direction intersecting the first direction.

21. The method according to claim 20 , wherein the recessing the first layer and the second layer via the hole includes:

forming a first member at a lower part of the hole, the first part of the hole being located in the lower part, and the second part of the hole being located above the lower part,

recessing the second layer via the hole,

removing the first member, and

recessing the first layer via the hole.

22. The method according to claim 20 , wherein

an impurity concentration of the second layer is higher than an impurity concentration of the first layer.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 7, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058664/0198 →
CHANGE OF NAME Recorded Jan 7, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058664/0544 →
Continuity (5)
Continuation 16707960 · Dec 9, 2019
Continuation 16049151 · Jul 30, 2018
Continuation 15460536 · Mar 16, 2017
Provisional Application 62376740 · Aug 18, 2016
Related Publication 20210134822A1 · May 6, 2021