Integrated circuit structure with front side signal lines and backside power delivery
Integrated circuit structures having front side signal lines and backside power delivery are described. In an example, an integrated circuit structure includes a plurality of gate lines extending over a plurality of semiconductor nanowire stack or fin channel structures within a cell boundary. A plurality of trench contacts is extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A first signal line, a second signal line, a third signal line, and a fourth signal line are over the plurality of gate lines and the plurality of trench contacts within the cell boundary. A backside power delivery line is coupled to one of the plurality of trench contacts within the cell boundary.
1. An integrated circuit structure, comprising:
a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures within a cell boundary, the plurality of gate lines having a pitch;
a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch; and
a backside power delivery line beneath the plurality of semiconductor nanowire stack channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.
2. The integrated circuit structure of claim 1 , wherein the backside power delivery line is coupled to the one or more of the plurality of trench contacts by a through-silicon via.
3. The integrated circuit structure of claim 1 , wherein one of the first, second, third and fourth signal lines is coupled to one of the plurality of gate lines over one of the plurality of semiconductor nanowire stack channel structures from a plan view perspective.
4. The integrated circuit structure of claim 1 , further comprising:
a plurality of conductive lines above the first, second, third and fourth signal lines within the cell boundary, the plurality of conductive lines having the pitch.
5. The integrated circuit structure of claim 1 , wherein an end-to-end (ETE) of the cell boundary is centered on the plurality of gate lines.
6. The integrated circuit structure of claim 1 , wherein an end-to-end (ETE) of the cell boundary is centered on the plurality of trench contacts.
7. An integrated circuit structure, comprising:
a plurality of gate lines extending over a plurality of semiconductor fin channel structures within a cell boundary, the plurality of gate lines having a pitch;
a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch; and
a backside power delivery line beneath the plurality of semiconductor fin channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.
8. The integrated circuit structure of claim 7 , wherein the backside power delivery line is coupled to the one or more of the plurality of trench contacts by a through-silicon via.
9. The integrated circuit structure of claim 7 , wherein one of the first, second, third and fourth signal lines is coupled to one of the plurality of gate lines over one of the plurality of semiconductor fin channel structures from a plan view perspective.
10. The integrated circuit structure of claim 7 , further comprising:
a plurality of conductive lines above the first, second, third and fourth signal lines within the cell boundary, the plurality of conductive lines having the pitch.
11. The integrated circuit structure of claim 7 , wherein an end-to-end (ETE) of the cell boundary is centered on the plurality of gate lines.
12. The integrated circuit structure of claim 7 , wherein an end-to-end (ETE) of the cell boundary is centered on the plurality of trench contacts.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate lines extending over a plurality of semiconductor nanowire stack channel structures within a cell boundary, the plurality of gate lines having a pitch;
a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch; and
a backside power delivery line beneath the plurality of semiconductor nanowire stack channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , further comprising:
a camera coupled to the board.
17. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.
18. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate lines extending over a plurality of semiconductor fin channel structures within a cell boundary, the plurality of gate lines having a pitch;
a plurality of trench contacts extending over a plurality of source or drain structures within the cell boundary, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines;
a first signal line, a second signal line, a third signal line, and a fourth signal line over the plurality of gate lines and the plurality of trench contacts within the cell boundary, the first, second, third and fourth signal lines having a minimum pitch of 1.5 times the pitch; and
a backside power delivery line beneath the plurality of semiconductor fin channel structures and the plurality of source or drain structures, the backside power delivery line coupled to one of the plurality of trench contacts within the cell boundary.
19. The computing device of claim 18 , further comprising:
a memory coupled to the board.
20. The computing device of claim 18 , further comprising:
a communication chip coupled to the board.
21. The computing device of claim 18 , further comprising:
a camera coupled to the board.
22. The computing device of claim 18 , wherein the component is a packaged integrated circuit die.