Non-volatile programmable logic device based on multi-chip package
A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.
1 . A multichip package comprising:
a first interconnection scheme comprising a first insulating dielectric layer, a first interconnection metal layer over the first insulating dielectric layer and a second insulating dielectric layer over the first interconnection metal layer and first insulating dielectric layer;
a plurality of first metal bumps at a bottom of the multichip package and under and in contact with the first interconnection scheme;
a first semiconductor chip over the first interconnection scheme, wherein the first interconnection scheme extends horizontally across under a right edge of the first semiconductor chip, wherein the first semiconductor chip comprises a first metal pad at a top of the first semiconductor chip and a first polymer layer at the top of the first semiconductor chip and in contact with a sidewall of the first metal pad;
a second polymer layer over the first interconnection scheme, at a first horizontal level same as the first semiconductor chip and in contact with a sidewall of the first semiconductor chip;
a metal post vertically in the second polymer layer, over and coupling to the first interconnection scheme and at the first horizontal level, wherein the metal post provides vertical connection and has a sidewall in contact with the second polymer layer;
a second interconnection scheme over the first semiconductor chip, second polymer layer and metal post, wherein the second interconnection scheme extends horizontally across over the right edge of the first semiconductor chip and couples vertically to the first interconnection scheme through the metal post, wherein the second interconnection scheme comprises a third insulating dielectric layer at a top of the second interconnection scheme and over the first semiconductor chip and second polymer layer, and the second interconnection scheme further comprises a plurality of second metal pads at the top of the second interconnection scheme, wherein each of the plurality of second metal pads has a first portion in an opening in the third insulating dielectric layer and a second portion over the opening in the third insulating dielectric layer and on a top surface of the third insulating dielectric layer, wherein said each of the plurality of second metal pads comprises a first copper layer and a first adhesion metal layer at a bottom of the first copper layer; and
a first chip-over-chip package over and coupling to the second interconnection scheme, wherein the first chip-over-chip package comprises a second semiconductor chip, a third semiconductor chip over the second semiconductor chip and a third polymer layer at a second horizontal level same as the third semiconductor chip, wherein a left sidewall of the third polymer layer at a left edge of the first chip-over-chip package is vertically over the second interconnection scheme and has a first horizontal distance from a left sidewall of the second polymer layer at a left edge of the multichip package, wherein the first chip-over-chip package comprises a plurality of second metal bumps at a bottom of the first chip-over-chip package and each bonded to one of the plurality of second metal pads.
2 . The multichip package of claim 1 , wherein the first insulating dielectric layer is at a bottom of the first interconnection scheme and a plurality of openings in the first insulating dielectric layer are under the first interconnection metal layer, wherein each of the plurality of first metal bumps has an upper portion in one of the plurality of openings in the first insulating dielectric layer and under and in contact with a bottom surface of the first interconnection metal layer and a lower portion under said one of the plurality of openings in the first insulating dielectric layer and under and in contact with a bottom surface of the first insulating dielectric layer.
3 . The multichip package of claim 1 , wherein each of the plurality of first metal bumps comprises a second copper layer having a thickness between 1 and 10 micrometers.
4 . The multichip package of claim 3 , wherein said each of the plurality of first metal bumps further comprises a second adhesion metal layer at a top of the second copper layer, wherein the second adhesion metal layer comprises titanium.
5 . The multichip package of claim 1 , wherein the plurality of first metal bumps comprise twelve metal bumps arranged in a line, at the bottom of the multichip package and under and in contact with the first interconnection scheme and the plurality of second metal pads comprise twelve metal pads arranged in a line and each vertically aligned with one of the twelve metal bumps.
6 . The multichip package of claim 1 , wherein each of the plurality of first metal bumps comprises tin.
7 . The multichip package of claim 1 , wherein the first copper layer of said each of the plurality of second metal pads has a thickness between 20 and 100 micrometers.
8 . The multichip package of claim 1 , wherein the metal post comprises a second copper layer having a thickness between 5 and 300 micrometers.
9 . The multichip package of claim 1 , wherein the metal post comprises a second copper layer having a thickness between 10 and 100 micrometers.
10 . The multichip package of claim 1 , wherein the first interconnection metal layer comprises a second copper layer and a second adhesion metal layer at a top of the second copper layer, wherein the second adhesion metal layer is not at a sidewall of the second copper layer.
11 . The multichip package of claim 1 , wherein the plurality of first metal bumps comprises a metal bump vertically under the first semiconductor chip and coupling to one of the plurality of second metal pads vertically over the first semiconductor chip through the metal post.
12 . The multichip package of claim 1 , wherein the first semiconductor chip extends horizontally across under the left sidewall of the third polymer layer and the first chip-over-chip package extends horizontally across over the right edge of the first semiconductor chip and couples to the first semiconductor chip.
13 . The multichip package of claim 1 , wherein the first chip-over-chip package is vertically over and couples to the metal post.
14 . The multichip package of claim 1 , wherein the first interconnection scheme, first semiconductor chip, second polymer layer, metal post and second interconnection scheme are provided by a base element, wherein the plurality of second metal bumps are bonded to the base element.
15 . The multichip package of claim 1 , wherein the plurality of first metal bumps are configured to be bonded and coupled to a circuit board and a plurality of solder balls are configured to be arranged in an array on a bottom surface of the circuit board.
16 . The multichip package of claim 1 further comprising a second chip-over-chip package over and bonded to the second interconnection scheme and at a third horizontal level same as the first chip-over-chip package, wherein the second chip-over-chip package comprises a third metal bump at a bottom of the second chip-over-chip package and bonded to one of the plurality of second metal pads.
17 . The multichip package of claim 16 , wherein the second chip-over-chip package comprises a fourth semiconductor chip, a fifth semiconductor chip over the fourth semiconductor chip and a fourth polymer layer at a fourth horizontal level same as the fifth semiconductor chip, wherein a right sidewall of the fourth polymer layer at a right edge of the second chip-over-chip package is vertically over the second interconnection scheme and has a second horizontal distance from a right sidewall of the second polymer layer at a right edge of the multichip package, wherein the right sidewall of the fourth polymer layer has a third horizontal distance from the left sidewall of the third polymer layer.
18 . The multichip package of claim 1 , wherein a first one of the plurality of second metal bumps is bonded to a first one of the plurality of second metal pads and coupled to the first metal pad of the first semiconductor chip and a second one of the plurality of second metal bumps is bonded to a second one of the plurality of second metal pads and coupled to the metal post.
19 . The multichip package of claim 1 further comprising a fourth semiconductor chip between the first and second interconnection schemes, at the first horizontal level and coupling to the second interconnection scheme.
20 . The multichip package of claim 19 further comprising a second chip-over-chip package over and coupling to the second interconnection scheme, wherein the second chip-over-chip package is at a third horizontal level same as the first chip-over-chip package, wherein the second chip-over-chip package comprises a third metal bump at a bottom of the second chip-over-chip package and bonded to one of the plurality of second metal pads, wherein the second chip-over-chip package extends horizontally across over an edge of the fourth semiconductor chip.
21 . The multichip package of claim 1 , wherein the second interconnection scheme further comprises a fourth insulating dielectric layer on the first semiconductor chip and second polymer layer and under the third insulating dielectric layer, wherein the fourth insulating dielectric layer extends horizontally across over the right edge of the first semiconductor chip, wherein a first opening in the fourth insulating dielectric layer is vertically over the first metal pad and a second opening in the fourth insulating dielectric layer is vertically over the metal post, wherein the second interconnection scheme further comprises a second interconnection metal layer on a top surface of the fourth insulating dielectric layer and under the third insulating dielectric layer, wherein the second interconnection metal layer is further in the first opening in the fourth insulating dielectric layer and in contact with the first metal pad and the second interconnection metal layer is further in the second opening in the fourth insulating dielectric layer and in contact with the metal post.
22 . The multichip package of claim 1 , wherein the first interconnection scheme comprises a first metal interconnect extending horizontally across under the right edge of the first semiconductor chip and the second interconnection scheme comprises a second metal interconnect extending horizontally across over the right edge of the first semiconductor chip, wherein one of the plurality of first metal bumps is vertically under the first semiconductor chip and couples to the second metal interconnect through, in sequence, the first metal interconnect and metal post.
23 . The multichip package of claim 1 , wherein the first semiconductor chip further comprises a silicon substrate, a semiconductor device at a top of the silicon substrate and a third interconnection scheme over the silicon substrate, wherein the semiconductor device comprises a capacitor.
24 . The multichip package of claim 1 , wherein the first metal pad comprises a second copper layer having a thickness between 1 and 10 micrometers.
25 . The multichip package of claim 1 , wherein the second polymer layer comprises a molding compound.
26 . The multichip package of claim 1 , wherein the third polymer layer comprises a molding compound.
27 . The multichip package of claim 1 , wherein the first interconnection scheme comprises a ground plane of a power supply.
28 . The multichip package of claim 1 , wherein the first interconnection scheme comprises a power plane of a power supply.
29 . The multichip package of claim 1 , wherein one of the second and third semiconductor chips is a memory chip.
30 . The multichip package of claim 29 , wherein the memory chip is a dynamic-random-access-memory (DRAM) chip.
31 . The multichip package of claim 1 , wherein the first chip-over-chip package further comprises a memory chip over the third semiconductor chip.