IP Library Granted Patent US 11,683,888
Granted Patent B2
US 11,683,888 · App. 17/218,556 · Granted Jun 20, 2023

Method for manufacturing a packaged circuit structure

Inventors: Chun-Chieh Huang (Taoyuan, TW); Chin-Ming Liu (Taoyuan, TW)
Assignees: Leading Interconnect Semiconductor Technology Qinhuangdao Co, Ltd.; Qi Ding Technology Qinhuangdao Co, Ltd.; Leading Interconnect Semiconductor Technology (ShenZhen) Co, Ltd.
H05K1/186H05K3/284H05K3/4697H05K2203/308
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Quick Facts
Patent No.
US 11,683,888
App. No.
17/218,556
Granted
Jun 20, 2023
Kind
B2
Abstract

A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.

Claims (23)

1. A method for manufacturing a package circuit structure comprising:

providing a multilayer circuit board comprising an opening area extending from a first side of the multilayer circuit board to a second side of the multilayer circuit board facing away from the first side along a thickness direction, and a metal portion corresponding to a bottom of the opening area to support the opening area, wherein the multilayer circuit board is manufacturing by the following steps:

providing a core board comprising a first metal foil, an inner dielectric layer, and a second metal foil stacked in that order along a thickness direction;

forming an inner circuit board by performing a circuit manufacturing technology on the core board, wherein the first metal foil correspondingly forms a first inner wiring layer, the second metal foil correspondingly forms a second inner wiring layer, the first inner wiring layer is electrically connected to the second inner wiring layer, the first inner wiring layer comprises a metal portion;

forming a first outer circuit board on the first inner wiring layer, and forming a second outer circuit board on the second inner wiring layer, wherein the first outer circuit board comprises a first outer dielectric layer combined with the first inner wiring layer and a first outer wiring layer formed on a side of the first outer dielectric layer facing away from the inner circuit board, the second outer circuit board comprises a second outer dielectric layer combined with the second inner wiring layer and a second outer wiring layer formed on a side of the second outer dielectric layer facing away from the inner circuit board, the second outer wiring layer comprises a second gap corresponding to the metal portion; and

forming a solder mask on each of a side of the first outer circuit board facing away from the inner circuit board and a side of the second outer circuit board facing away from the inner circuit board;

removing the opening area to form an opening, wherein a bottom of the opening is sealed by the metal portion;

installing an electronic component in the opening, wherein the electronic component is carried by the metal portion and electrically connected to the multilayer circuit board; and

packaging the electronic component.

2. The method of claim 1 , wherein before removing the opening area to form the opening, further comprising:

forming a protective film on each of the first side of the multilayer circuit board and the second side of the multilayer circuit board, wherein the opening area is exposed from the protective film on the first side of the multilayer circuit board;

after removing the opening area to form the opening, further comprising:

removing the protective films.

3. The method of claim 1 , wherein no wiring is provided in the opening area, the multilayer circuit board further comprises two solder masks on opposite sides of the multilayer circuit board along the thickness direction respectively, the opening area is exposed from the solder mask on the first side.

4. The method of claim 1 , wherein the second inner wiring layer comprises a first gap corresponding to the metal portion.

5. The method of claim 4 , wherein a size of the first gap is greater than a size of the metal portion.

6. The method of claim 1 , wherein a size of the second gap is greater than a size of the metal portion.

7. The method of claim 1 , wherein the solder mask on the side of the second outer circuit board facing away from the inner circuit board comprises a third gap corresponding to the metal portion.

8. The method of claim 7 , wherein a size of the third gap is greater than a size of the metal portion.

9. The method of claim 1 , wherein a width of the opening decreases from the first side of the multilayer circuit board toward the second side of the multilayer circuit board.

10. The method of claim 1 , wherein packaging the electronic component further comprising:

forming an insulating layer on the first side of the multilayer circuit board, wherein the insulating fills the opening and covers the electronic component.

11. The method of claim 10 , wherein the insulating layer is formed by injection molding.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2024
From: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
Reel/Frame 066191/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2023
From: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
Reel/Frame 062848/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2021
From: HUANG, CHUN-CHIEH; LIU, CHIN-MING
To: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
Reel/Frame 055781/0632 →
Priority Claims (1)
CN 202110097582.X · Jan 25, 2021 · national
Continuity (1)
Related Publication 20220240385A1 · Jul 28, 2022