IP Library Granted Patent US 11,887,984
Granted Patent B2
US 11,887,984 · App. 17/224,617 · Granted Jan 30, 2024

Complementary transistor and semiconductor device

Inventors: Hidetoshi Oishi (Saga, JP); Koichi Matsumoto (Kanagawa, JP); Kazuyuki Tomida (Kanagawa, JP)
Assignee: Sony Group Corporation
H01L27/0924H01L21/26506H01L21/823807H01L21/823821H01L21/84H01L27/092H01L27/1203H01L29/0649H01L29/1054H01L29/16H01L29/1606H01L29/24H01L29/267H01L29/41791H01L29/4232H01L29/66045H01L29/66795H01L29/7391H01L29/778H01L29/7851H01L29/78618H01L29/78639H01L29/78681H01L29/78684H01L29/78696H10B10/00
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Quick Facts
Patent No.
US 11,887,984
App. No.
17/224,617
Granted
Jan 30, 2024
Kind
B2
Abstract

A complementary transistor is constituted of a first transistor TR 1 and a second transistor TR 2 , active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 20 1 , 20 2 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43 , and extension layers 36, 46 of the first B layer are provided on insulation regions 21 1 ,21 2 respectively.

Claims (87)

1. A complementary transistor, comprising:

a semiconductor substrate;

a first transistor including:

a first control electrode;

a first active region located below the first control electrode;

a first A extension region extending from one end of the first active region;

a first B extension region extending from the other end of the first active region; and

a buffer layer provided between the first control electrode and the semiconductor substrate; and

a second transistor including:

a second control electrode;

a second active region located below the second control electrode;

a second A extension region extending from one end of the second active region; and

a second B extension region extending from the other end of the second active region.

2. The complementary transistor according to claim 1 , wherein the buffer layer includes a material selected from a group consisting of InP, InAlAs, InGaAs, GaAs, and GaSb.

3. The complementary transistor according to claim 1 , wherein

the first A extension region and the second A extension region are constituted of different materials, and

the first B extension region and the second B extension region are constituted of a same material.

4. The complementary transistor according to claim 1 , wherein

the first A extension region and the second A extension region are constituted of different materials, and

the first B extension region and the second B extension region are constituted of different materials.

5. The complementary transistor according to claim 1 , wherein

the first B extension region is constituted of a two-dimensional material or graphene, and

the second B extension region is constituted of a two-dimensional material or graphene.

6. The complementary transistor according to claim 5 , wherein the two-dimensional material includes one kind of two-dimensional material selected from a group consisting of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, ZrTe2, HfS2, HfSe2 and HfTe2.

7. The complementary transistor according to claim 1 , wherein

the first A extension region has a first conductivity type,

the first B extension region has a second conductivity type different from the first conductivity type,

the second A extension region has the second conductivity type, and

the second B extension region has the first conductivity type.

8. The complementary transistor according to claim 1 , further comprising:

a first A electrode connected to the first A extension region,

a first B electrode connected to the first B extension region,

a second A electrode connected to the second A extension region, and

a second B electrode connected to the second B extension region.

9. The complementary transistor according to claim 1 , further comprising a first element isolation region provided between the semiconductor substrate and the first B extension region and a second element isolation region provided between the semiconductor substrate and the second B extension region.

10. The complementary transistor according to claim 9 , wherein the first and second element isolation regions include SiO2.

11. The complementary transistor according to claim 1 , further comprising a first insulating layer provided between the first control electrode and the first active region and a second insulating layer provided between the second control electrode and the second active region.

12. The complementary transistor according to claim 11 , wherein the first and second insulating layers include HfO2.

13. The complementary transistor according to claim 1 , wherein the first active region includes a first A layer and a first B layer and the second active region includes a second A layer and a second B layer.

14. The complementary transistor according to claim 13 , further comprising:

a first interlayer insulation film formed between the first A layer and the first B layer, and

a second interlayer insulation film formed between the second A layer and the second B layer.

15. A complementary transistor, comprising:

a semiconductor substrate;

a first transistor including:

a first control electrode;

a first boundary region located below the first control electrode and formed by a first B layer;

a first A extension layer extending from one end of the first boundary region;

a first B extension layer of the first B layer extending from the other end of the first boundary region;

a second transistor including:

a second control electrode;

a second boundary region located below the second control electrode and formed by

a second B layer;

a second A extension layer extending from one end of the second boundary region; and

a second B extension layer of the second B layer extending from the other end of the second boundary region;

a first element isolation region provided between the semiconductor substrate and the first boundary region,

wherein the first element isolation region is provided under the first B layer and the first B extension layer; and

a second element isolation region provided between the semiconductor substrate and the second boundary region,

wherein the second element isolation region is provided under the second B layer and the second B extension layer.

16. The complementary transistor according to claim 15 , wherein

the first A extension layer and the second A extension layer are constituted of different materials, and

the first B extension layer and the second B extension layer are constituted of a same material.

17. The complementary transistor according to claim 15 , wherein

the first B extension layer is constituted of a two-dimensional material or graphene, and

the second B extension layer is constituted of a two-dimensional material or graphene.

18. A complementary transistor, comprising:

a semiconductor substrate;

a first transistor including:

a first control electrode;

a first boundary region located below the first control electrode and formed by a first

B layer;

a first A extension layer extending from one end of the first boundary region;

a first B extension layer of the first B layer extending from the other end of the first boundary region;

a second transistor including:

a second control electrode;

a second boundary region located below the second control electrode and formed by a second B layer;

a second A extension layer extending from one end of the second boundary region; and

a second B extension layer of the second B layer extending from the other end of the second boundary region;

a first element isolation region provided within the semiconductor substrate, wherein the first element isolation region is provided under the first B layer and the first B extension layer; and

a second element isolation region provided within the semiconductor substrate,

wherein the second element isolation region is provided under the second B layer and the second B extension layer.

19. The complementary transistor according to claim 18 , wherein

the first A extension layer and the second A extension layer are constituted of different materials, and

the first B extension layer and the second B extension layer are constituted of a same material.

20. The complementary transistor according to claim 18 , wherein

the first B extension layer is constituted of a two-dimensional material or graphene, and

the second B extension layer is constituted of a two-dimensional material or graphene.

Assignments (3)
CHANGE OF NAME Recorded Sep 17, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 057538/0224 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 55864 FRAME: 412. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2021
From: OISHI, HIDETOSHI; MATSUMOTO, KOICHI; TOMIDA, KAZUYUKI
To: SONY CORPORATION
Reel/Frame 057392/0458 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2021
From: OISHI, HIDETOSHI; MATSUMOTO, KOICHI; TOMIDA, KAZUYUKI
To: SONY GROUP CORPORATION
Reel/Frame 055854/0412 →
Priority Claims (2)
JP 2016-142699 · Jul 20, 2016 · national
JP 2017-118682 · Jun 16, 2017 · national
Continuity (3)
Continuation 16893280 · Jun 4, 2020
Continuation 16316702
Related Publication 20210225841A1 · Jul 22, 2021