Semiconductor device
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.
1. A semiconductor device comprising:
a transistor comprising:
an oxide semiconductor layer comprising a channel formation region;
a first electrode layer below the channel formation region of the oxide semiconductor configured to function as one of a source electrode and a drain electrode; and
a second electrode layer above the channel formation region of the oxide semiconductor configured to function as the other of the source electrode and the drain electrode;
a capacitor comprising:
a dielectric layer;
the first electrode layer below the dielectric layer; and
a third electrode layer above the dielectric layer;
a first layer providing the first electrode layer;
a first insulating layer over the first layer;
a conductive layer over the first insulating layer;
a second insulating layer over the conductive layer;
a second layer over the second insulating layer, the second layer providing the second electrode layer and the third electrode layer;
a first opening and a second opening each penetrating the first insulating layer, the conductive layer and the second insulating layer;
a third insulating layer in contact with a sidewall of the first opening; and
a fourth insulating layer in contact with a sidewall of the second opening,
wherein the oxide semiconductor layer and the third insulating layer are embedded in the first opening,
wherein the dielectric layer and the fourth insulating layer are embedded in the second opening, and
wherein a channel direction of the transistor is perpendicular to a top surface of a substrate.
2. The semiconductor device according to claim 1 ,
wherein the transistor further comprises:
a gate insulating layer included in a region of the third insulating layer; and
a gate electrode layer included in a region of the conductive layer.
3. The semiconductor device according to claim 2 , wherein in a plan view, the conductive layer comprises a region surrounding the oxide semiconductor layer.
4. The semiconductor device according to claim 2 , wherein the first electrode layer comprises a conductive material comprising polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, chromium, nickel, or molybdenum.
5. The semiconductor device according to claim 2 ,
wherein the gate insulating layer comprises silicon oxide, silicon nitride oxide, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate, hafnium silicate to which nitrogen is added, or hafnium aluminate to which nitrogen is added, and
wherein the gate insulating layer has a single-layer structure or a stacked structure.
6. The semiconductor device according to claim 1 , wherein the transistor is a vertical transistor.
7. The semiconductor device according to claim 1 , wherein the first electrode layer comprises a conductive material comprising polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, chromium, nickel, or molybdenum.
8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor layer comprises a crystal portion, and
wherein c-axis of the crystal portion is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed or to a surface of the first electrode layer.
9. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has a prismatic shape or a cylindrical shape.
10. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.
11. The semiconductor device according to claim 1 , wherein direction perpendicular to the top surface of the substrate is in the range of 85° or more and 95° or less with respect to the upper surface of the substrate.
12. A semiconductor device comprising:
a first layer;
a first insulating layer over the first layer;
a conductive layer over the first insulating layer;
a second insulating layer over the conductive layer;
a second layer over the second insulating layer;
a first opening and a second opening each penetrating the first insulating layer, the conductive layer and the second insulating layer;
a third insulating layer in contact with a sidewall of the first opening;
a fourth insulating layer in contact with a sidewall of the second opening;
a transistor comprising:
an oxide semiconductor layer embedded in the first opening, the oxide semiconductor layer comprising a first region, a second region and a third region;
a first electrode layer configured to function as one of a source electrode and a drain electrode in contact with the first region of the oxide semiconductor; and
a second electrode layer configured to function as the other of the source electrode and the drain electrode in contact with the second region of the oxide semiconductor; and
a capacitor comprising:
a dielectric layer embedded in the second opening;
the first electrode layer configured to function as a first electrode of the capacitor; and
a third electrode layer in the second layer, the third electrode layer configured to function as a second electrode of the capacitor,
wherein the first region of the oxide semiconductor layer is located below than the third region of the oxide semiconductor layer,
wherein the second region of the oxide semiconductor layer is located above than the third region of the oxide semiconductor layer, and
wherein a channel direction is perpendicular to a top surface of a substrate.
13. The semiconductor device according to claim 12 ,
wherein the transistor further comprises;
a gate insulating layer included in a region of the third insulating layer; and
a gate electrode layer included in a region of the conductive layer.
14. The semiconductor device according to claim 13 , wherein in a plan view, the conductive layer comprises a region surrounding the oxide semiconductor layer.
15. The semiconductor device according to claim 13 , wherein the first electrode layer comprises a conductive material comprising polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, chromium, nickel, or molybdenum.
16. The semiconductor device according to claim 13 ,
wherein the gate insulating layer comprises silicon oxide, silicon nitride oxide, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate, hafnium silicate to which nitrogen is added, or hafnium aluminate to which nitrogen is added, and
wherein the gate insulating layer has a single-layer structure or a stacked structure.
17. The semiconductor device according to claim 12 , wherein the transistor is a vertical transistor.
18. The semiconductor device according to claim 12 , wherein the first electrode layer comprises a conductive material comprising polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, chromium, nickel, or molybdenum.
19. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor layer comprises a crystal portion, and
wherein c-axis of the crystal portion is aligned in a direction parallel to a normal vector of a surface where the oxide semiconductor layer is formed or to a surface of the first electrode layer.
20. The semiconductor device according to claim 12 , wherein the oxide semiconductor layer has a prismatic shape or a cylindrical shape.
21. The transistor according to claim 12 ,
wherein the oxide semiconductor layer comprises at least one of indium and zinc.
22. The transistor according to claim 12 ,
wherein direction perpendicular to the top surface of the substrate is in the range of 85° or more and 95° or less with respect to the upper surface of the substrate.