Glass-based cavity and channels for cooling of embedded dies and 3D integrated modules using package substrates with glass core
Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.
1 . A package substrate, comprising:
a core with a first surface and a second surface opposite from the first surface;
a buildup layer over the first surface of the core;
a channel having a first portion through the core along a horizonal direction, and a second portion through the buildup layer along a vertical direction, wherein a first terminal end of the channel is in vertical alignment with a sidewall of the core, and wherein a second terminal end of the channel is at a top of the buildup layer;
a die coupled to the top of the build-up layer;
a first inlet/outlet at the first terminal end of the channel, the first inlet/outlet on the sidewall of the core and outside of a footprint of the die; and
a second inlet/outlet at the second terminal end of the channel and laterally spaced apart from the die.
2 . The package substrate of claim 1 ,
wherein sidewalls of the second portion of the channel are lined with a barrier layer.
3 . The package substrate of claim 1 , further comprising:
through core vias between the first surface of the core and the second surface of the core.
4 . The package substrate of claim 3 , wherein the through core vias have an hourglass shaped cross-section, and wherein at least one of the through core vias is a via plane.
5 . The package substrate of claim 1 , wherein the core is a glass core.
6 . A package substrate, comprising:
a core with a first surface and a second surface opposite from the first surface;
a buildup layer over the first surface of the core;
a plurality of channels through the core, wherein the plurality of channels are at a depth within the core between the first surface and the second surface, and wherein one of the channels has a first portion through the core along a horizontal direction, and a second portion through the buildup layer along a vertical direction, wherein a first terminal end of the one of the channels is in vertical alignment with a sidewall of the core, and wherein a second terminal end of the one of the channels is at a top of the buildup layer;
a die coupled to the top of the build-up layer;
a first inlet/outlet at the first terminal end of the one of the channels, the first inlet/outlet on the sidewall of the core and outside of a footprint of the die; and
a second inlet/outlet at the second terminal end of the one of the channels and laterally spaced apart from the die.
7 . The package substrate of claim 6 , wherein the plurality of channels are substantially parallel to each other.
8 . The package substrate of claim 6 , wherein the plurality of channels have a first pitch at a first end of the plurality of channels, and wherein the plurality of channels have a second pitch that is smaller than the first pitch at a location between the first end of the plurality of channels and a second end of the plurality of channels.
9 . The package substrate of claim 6 , wherein the core is a glass core.
10 . The package substrate of claim 6 , wherein through core vias pass through a thickness of the core adjacent to one or more of the plurality of channels.
11 . The package substrate of claim 10 , wherein the through core vias have a cross-section that is hourglass shaped.
12 . The package substrate of claim 6 , further comprising: buildup layers below the core.
13 . The package substrate of claim 12 , wherein holes through the buildup layers connect to the plurality of channels, and wherein the holes are lined with a barrier layer.
14 . An electronic system, comprising:
a board;
a package substrate coupled to the board, wherein the package substrate comprises:
a core;
a buildup layer over the first surface of the core; and
channels through the core, wherein one of the channels has a first portion through the core along a horizontal direction, and a second portion through the buildup layer along a vertical direction, wherein a first terminal end of the one of the channels is in vertical alignment with a sidewall of the core, and wherein a second terminal end of the one of the channels is at a top of the buildup layer;
a die coupled to the top of the buildup layer of the package substrate, wherein a footprint of the die is provided over a portion of the channels;
a first inlet/outlet at the first terminal end of the one of the channels, the first inlet/outlet on the sidewall of the core and outside of a footprint of the die; and
a second inlet/outlet at the second terminal end of the one of the channels and laterally spaced apart from the die.
15 . The electronic system of claim 14 , wherein the core is a glass core.
16 . The electronic system of claim 14 , wherein the channels have a first pitch outside of the footprint of the die and a second pitch that is smaller than the first pitch within the footprint of the die.
17 . The electronic system of claim 14 , wherein second ends of the channels are on the top surface of the core.