IP Library › Granted Patent US 12,185,538
Granted Patent B2
US 12,185,538 · App. 17/398,654 · Granted Dec 31, 2024

Semiconductor memory device with a three-dimensional stacked memory cell structure

Inventors: Tomoo Hishida (Yokohama, JP); Yoshihisa Iwata (Yokohama, JP)
Assignee: Kioxia Corporation
H10B43/27G11C5/025G11C5/063G11C7/18G11C8/12G11C16/0483H01L23/528H01L29/7926H10B43/30H10B43/50G11C5/04G11C2213/71H01L2924/0002
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Quick Facts
Patent No.
US 12,185,538
App. No.
17/398,654
Granted
Dec 31, 2024
Kind
B2
Abstract

A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Claims (80)

1. A semiconductor memory device, comprising:

a first memory unit including a first memory cell and a second memory cell stacked in a first direction;

a second memory unit including a third memory cell and a fourth memory cell stacked in the first direction, the second memory unit being aligned separately from the first memory unit in a second direction, the second direction being perpendicular to the first direction;

a third memory unit including a fifth memory cell and a sixth memory cell stacked in the first direction, the third memory unit being provided separately from the first memory unit in a third direction, the third direction being perpendicular to the first direction and the second direction; a first bit line extending in the second direction, the first bit line being provided above the first memory unit and the second memory unit;

a second bit line extending in the second direction, the second bit line being provided above the first memory unit and the second memory unit and adjacent to the first bit line in the third direction;

a third bit line extending in the second direction, the third bit line being provided above the third memory unit and adjacent to the first bit line in the third direction;

a first contact connected to the first bit line and the first memory unit;

a second contact connected to the second bit line and the second memory unit;

a third contact connected to the third bit line and the third memory unit; and

a first conductive layer extending in the second direction and the third direction, and comprising a gate of the first memory cell and a gate of the third memory cell,

wherein the third bit line does not overlap the first memory unit and the second memory unit in the first direction.

2. The semiconductor memory device according to claim 1 further comprising:

a fourth memory unit including a seventh memory cell and an eighth memory cell stacked in the first direction, the fourth memory unit being provided separately from the third memory unit in the second direction;

a fourth bit line extending in the second direction, the fourth bit line being provided above the third memory unit and the fourth memory unit and adjacent to the third bit line in the third direction; and

a fourth contact connected to the fourth bit line and the fourth memory unit.

3. The semiconductor memory device according to claim 2 ,

the first conductive layer comprising a gate of the fifth memory cell, and a gate of the seventh memory cell.

4. The semiconductor memory device according to claim 2 further comprising:

a second conductive layer comprising a gate of the fifth memory cell, and a gate of the seventh memory cell.

5. The semiconductor memory device according to claim 2 further comprising:

a third conductive layer extending in the third direction; and

a fourth conductive layer extending in the third direction,

the first memory unit further comprising a first transistor,

the second memory unit further comprising a second transistor,

the third memory unit further comprising a third transistor,

the fourth memory unit further comprising a fourth transistor,

the third conductive layer comprising a gate of the first transistor and the third transistor, and

the fourth conductive layer comprising a gate of the second transistor and the fourth transistor.

6. A semiconductor memory device, comprising:

a first memory unit including a first memory cell and a second memory cell stacked in a first direction;

a second memory unit including a third memory cell and a fourth memory cell stacked in the first direction, the second memory unit being provided separately from the first memory unit in a second direction, the second direction being perpendicular to the first direction, a gate of the first memory cell being electrically shared to a gate of the third memory cell;

a third memory unit including a fifth memory cell and a sixth memory cell stacked in the first direction, the third memory unit being provided separately from the first memory unit in a third direction, the third direction being perpendicular to the first direction and the second direction;

a first bit line extending in the second direction, the first bit line being provided above the first memory unit and the second memory unit;

a second bit line extending in the second direction, the second bit line being provided above the first memory unit and the second memory unit and adjacent to the first bit line in the third direction;

a third bit line extending in the second direction, the third bit line being provided above the third memory unit and adjacent to the first bit line in the third direction;

a first contact connected to the first bit line and the first memory unit;

a second contact connected to the second bit line and the second memory unit; and

a third contact connected to the third bit line and the third memory unit,

wherein the third bit line does not overlap the first memory unit and the second memory unit in the first direction.

7. The semiconductor memory device according to claim 6 further comprising:

a fourth memory unit including a seventh memory cell and an eighth memory cell stacked in the first direction, the fourth memory unit being provided separately from the third memory unit in the second direction, a gate of the fifth memory cell being electrically shared to a gate of the seventh memory cell;

a fourth bit line extending in the second direction, the fourth bit line being provided above the third memory unit and the fourth memory unit and adjacent to the third bit line in the third direction; and

a fourth contact connected to the fourth bit line and the fourth memory unit.

8. The semiconductor memory device according to claim 7 , the gate of the first memory cell being electrically shared to the gate of the third memory cell, the gate of the fifth memory cell, and the gate of the seventh memory cell.

9. The semiconductor memory device according to claim 7 further comprising:

the first memory unit further comprising a first transistor,

the second memory unit further comprising a second transistor,

the third memory unit further comprising a third transistor,

the fourth memory unit further comprising a fourth transistor,

a gate of the first transistor being electrically shared to a gate of the third transistor, and

a gate of the second transistor being electrically shared to a gate of the fourth transistor.

10. A semiconductor memory device, comprising:

a first memory unit including a first memory cell and a second memory cell stacked in a first direction;

a second memory unit including a third memory cell and a fourth memory cell stacked in the first direction, the second memory unit being provided separately from the first memory unit in a second direction, the second direction being perpendicular to the first direction;

a third memory unit including a fifth memory cell and a sixth memory cell stacked in the first direction, the third memory unit being provided separately from the first memory unit in a third direction, the third direction being perpendicular to the first direction and the second direction;

a first bit line extending in the second direction, the first bit line being provided above the first memory unit and the second memory unit;

a second bit line extending in the second direction, the second bit line being provided above the first memory unit and the second memory unit and adjacent to the first bit line in the third direction;

a third bit line extending in the second direction, the third bit line being provided above the third memory unit and adjacent to the first bit line in the third direction;

a first contact connected to the first bit line and the first memory unit;

a second contact connected to the second bit line and the second memory unit;

a third contact connected to the third bit line and the third memory unit; and

a first conductive layer connected to a gate of the first memory cell and a gate of the third memory cell,

wherein the third bit line does not overlap the first memory unit and the second memory unit in the first direction.

11. The semiconductor memory device according to claim 10 further comprising:

a fourth memory unit including a seventh memory cell and an eighth memory cell stacked in the first direction, the fourth memory unit being provided separately from the third memory unit in the second direction;

a fourth bit line extending in the second direction, the fourth bit line being provided above the third memory unit and the fourth memory unit and adjacent to the third bit line in the third direction; and

a fourth contact connected to the fourth bit line and the fourth memory unit.

12. The semiconductor memory device according to claim 11 ,

the first conductive layer being connected to a gate of the fifth memory cell, and a gate of the seventh memory cell.

13. The semiconductor memory device according to claim 11 further comprising:

a second conductive layer connected to a gate of the fifth memory cell, and a gate of the seventh memory cell.

14. The semiconductor memory device according to claim 11 further comprising:

a third conductive layer extending in the third direction; and

a fourth conductive layer extending in the third direction,

the first memory unit further comprising a first transistor,

the second memory unit further comprising a second transistor,

the third memory unit further comprising a third transistor,

the fourth memory unit further comprising a fourth transistor,

the third conductive layer connected to a gate of the first transistor and the third transistor, and

the fourth conductive layer connected to a gate of the second transistor and the fourth transistor.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 14, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058737/0945 →
CHANGE OF NAME Recorded Jan 14, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058738/0001 →
Priority Claims (1)
JP 2011-143500 · Jun 28, 2011 · national
Continuity (7)
Continuation 16694756 · Nov 25, 2019
Continuation 16047811 · Jul 27, 2018
Continuation 15388691 · Dec 22, 2016
Continuation 14727134 · Jun 1, 2015
Continuation 14307154 · Jun 17, 2014
Continuation 13423546 · Mar 19, 2012
Related Publication 20210375923A1 · Dec 2, 2021