Channel protection of gate-all-around devices for performance optimization
A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.
1. A semiconductor structure, comprising:
a plurality of channel layers vertically stacked over a substrate;
an inner spacer located between each of the plurality of channel layers;
source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers; and
a first dielectric layer located on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions, a width of the first dielectric layer and the second portion of the plurality of channel layers being equal to a width of the inner spacer located between each of the plurality of channel layers.
2. The semiconductor structure of claim 1 , further comprising:
a metal gate stack surrounding the plurality of channel layers and separated from the source/drain regions by the inner spacer.
3. The semiconductor structure of claim 2 , further comprising:
a first portion of a sidewall spacer surrounding the first dielectric layer and the inner spacer in the spacer region; and
a second portion of the sidewall spacer located along opposite sidewalls of the metal gate stack.
4. The semiconductor structure of claim 3 , further comprising:
a bottom dielectric isolation layer located between an uppermost surface of the substrate and a bottom surface of the source/drain regions and the metal gate stack, the bottom dielectric isolation layer isolating the source/drain regions and the metal gate stack from the substrate.
5. The semiconductor structure of claim 3 , further comprising:
source/drain contacts in contact with an uppermost surface of the source/drain regions, the source/drain contacts being separated from the metal gate stack by the second portion of the sidewall spacer.
6. The semiconductor structure of claim 1 , further comprises:
a portion of the substrate below the plurality of channel layers being located between shallow trench isolation regions.
7. The semiconductor structure of claim 6 , wherein a width of the plurality of channel layers is less than a width of the portion of the substrate located between the shallow trench isolation regions.
8. The semiconductor structure of claim 1 , wherein the first dielectric layer protects edges of the plurality of channel layers in the spacer region such that the edges of the plurality of channel layers have a substantially square shape.
9. The semiconductor structure of claim 1 , wherein the plurality of channel layers comprises at least one of a nanosheet, a nanowire, and a nano-ellipse.
10. A method of forming a semiconductor structure, comprising:
forming a plurality of channel layers vertically stacked over a substrate;
forming an inner spacer between each of the plurality of channel layers;
forming source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers; and
forming a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located on a spacer region that is adjacent to the source/drain regions, a width of the first dielectric layer and the second portion of the plurality of channel layers being equal to a width of the inner spacer located between each of the plurality of channel layers.
11. The method of claim 10 , further comprising:
forming a nanosheet stack on the substrate, the nanosheet stack comprising a nanosheet stack sacrificial layer above the substrate and an alternating sequence of sacrificial semiconductor nanosheets and channel layers from the plurality of channel layers;
patterning the nanosheet stack to form a nanosheet fin;
etching lateral portions of the plurality of channel layers to form an indentation region on opposite ends of the plurality of channel layers;
conformally depositing the first dielectric layer for pinching-off the indentation region;
forming a dummy gate on the nanosheet fin; and
selectively removing the nanosheet stack sacrificial layer from the nanosheet stack, wherein removing the nanosheet stack sacrificial layer creates an opening between the nanosheet fin and the substrate.
12. The method of claim 11 , further comprising:
conformally depositing a spacer material to form a sidewall spacer along opposite sidewalls of the dummy gate, the spacer material filling the opening between the nanosheet fin and the substrate;
removing portions of the spacer material above an uppermost channel layer of the plurality of channel layers; and
using the sidewall spacer along sidewalls of the dummy gate as a mask, etching the nanosheet fin in a way such that a remaining portion of the nanosheet fin is vertically aligned with the sidewall spacer.
13. The method of claim 12 , further comprising:
forming the inner spacer on opposite sides of the sacrificial semiconductor nanosheets;
epitaxially growing the source/drain regions; and
forming a second dielectric layer above the source/drain regions and between portions of the sidewall spacer adjacent to the source/drain regions.
14. The method of claim 13 , further comprising:
removing the dummy gate, wherein removing the dummy gate creates first recesses between the portions of the sidewall spacer adjacent to the source/drain regions;
selectively etching portions of the first dielectric layer located in contact with the sacrificial semiconductor nanosheets;
selectively removing the sacrificial semiconductor nanosheets; and
conducting a high-k pre-clean process that removes remaining portions of the first dielectric layer from a gate region.
15. The method of claim 14 , further comprising:
forming a metal gate stack within the first recesses, the metal gate stack surrounding the plurality of channel layers and being separated from the source/drain regions by the inner spacer.
16. The method of claim 15 , wherein a first portion of the sidewall spacer surrounds the first dielectric layer and the inner spacer on the spacer region, and a second portion of the sidewall spacer is located along opposite sidewalls of the metal gate stack.
17. The method of claim 16 , further comprising:
forming a bottom dielectric isolation layer between an uppermost surface of the substrate and a bottom surface of the source/drain region and the metal gate stack, the bottom dielectric isolation layer isolating the source/drain regions from the substrate.
18. The method of claim of claim 17 , further comprising:
forming source/drain contacts in contact with an uppermost surface of the source/drain regions, the source/drain contacts being separated from the metal gate stack by the bottom dielectric isolation layer.
19. The method of claim 10 , further comprising:
forming shallow trench isolation regions on opposite sides of a portion of the substrate located below the plurality of channel layers.
20. The method of claim 19 , wherein a width of the plurality of channel layers is less than a width of the portion of the substrate located between the shallow trench isolation regions.