Granted Patent B2

US 12,401,010 · App. 17/474,917 · Granted Aug 26, 2025

Inventors: Steven L. Teig (Menlo Park, CA); Ilyas Mohammed (Santa Clara, CA); Kenneth Duong (San Jose, CA); Javier DeLaCruz (San Jose, CA)

Assignee: Adeia Semiconductor Inc.

H01L25/18H01L24/92H01L25/0657H01L24/03H01L24/08H01L24/11H01L24/16H01L24/32H01L24/80H01L25/043H01L25/074H01L25/0756H01L25/105H01L25/117H01L25/16H01L2224/08145H01L2224/16145H01L2224/16225H01L2224/17181H01L2224/32145H01L2224/80895H01L2224/80896H01L2224/9202H01L2225/06503H01L2225/06548H10B41/20H10B51/20H10B53/20H10B63/84H10D88/00H10K19/201

Abstract

Claims (51)

1. A three dimensional (3D) processor circuit, comprising:

a first integrated circuit (IC) die comprising a first processor core; and

a second IC die vertically mounted on the first IC die, the second IC die comprising a first cache for the first processor core,

wherein the first cache vertically overlaps with at least a portion of the first processor core at an overlapping area, and

wherein the first IC die is communicatively coupled with the second IC die through a hybrid bond comprising a plurality of directly bonded metal contact pads and directly bonded non-conductive regions, and

wherein the first processor core is electrically connected to the first cache through at least one of the plurality of directly bonded metal contact pads disposed within the overlapping area.

2. The 3D processor circuit of claim 1 , further comprising a plurality of z-axis connections between the first processor core and the first cache.

3. The 3D processor circuit of claim 2 , wherein the plurality of z-axis connections comprises a z-axis bus, the z-axis bus being wholly defined within the overlapping area.

4. The 3D processor circuit of claim 2 , wherein at least two of the plurality of z-axis connections have a center-to-center pitch that is less than 5 microns.

5. The 3D processor circuit of claim 2 , wherein the plurality of z-axis connections comprises interconnect layers interconnecting the first processor core and the first cache through the hybrid bond.

6. The 3D processor circuit of claim 1 , wherein the first IC die and the second IC die are face-to-face mounted.

7. The 3D processor circuit of claim 1 , wherein:

the second IC die further comprises a second processor core;

the first IC die further comprises a second cache;

the second cache is for the second processor core; and

the second processor core vertically overlaps with the second cache.

8. The 3D processor circuit of claim 1 , wherein the first cache is an L1 cache.

9. The 3D processor circuit of claim 8 , wherein the first cache completely overlaps the first processor core.

10. The 3D processor circuit of claim 8 , further comprising a second cache on the first IC die for the first processor core.

11. The 3D processor circuit of claim 10 , wherein the second cache is an L2 cache.

12. The 3D processor circuit of claim 1 , wherein the 3D processor circuit excludes an L3 cache.

13. The 3D processor circuit of claim 1 , wherein the 3D processor circuit is a graphical processing unit.

14. The 3D processor circuit of claim 1 , wherein the 3D processor circuit is a central processing unit.

15. An electronic device, comprising: a three-dimensional (3D) processor circuit, comprising:

a first integrated circuit (IC) die comprising a first processor core;

a second IC die vertically mounted on the first IC die, the second IC die comprising a first cache for the first processor core,

wherein the first IC die is communicatively coupled with the second IC die through a hybrid bond comprising a plurality of directly bonded metal contact pads and directly bonded non-conductive regions,

wherein the first cache vertically overlaps with at least a portion of the first processor core at an overlapping area, and

wherein the first processor core is electrically connected to the first cache through at least one of the plurality of directly bonded metal contact pads disposed within the overlapping area; and

a board on which the 3D processor circuit is mounted.

16. The electronic device of claim 15 , further comprising a plurality of z-axis connections between the first processor core and the first cache.

17. The electronic device of claim 16 , wherein the plurality of z-axis connections comprises a z-axis bus, the z-axis bus being wholly defined within the overlapping area.

18. The 3D processor circuit of claim 16 , wherein the plurality of z-axis connections comprises interconnect layers interconnecting the first processor core and the first cache through the hybrid bond.

19. The electronic device of claim 15 , wherein the first IC die and the second IC die are face-to-face mounted.

20. The electronic device of claim 15 , wherein:

the second IC die further comprises a second processor core;

the first IC die further comprises a second cache;

the second cache is for the second processor core; and

the second processor core vertically overlaps with at least a portion of the second cache.

21. A three dimensional (3D) processor circuit, comprising:

a first integrated circuit (IC) die comprising a processor core;

a second IC die vertically stacked on the first IC die, the second IC die comprising a cache for the processor core; and

interconnect layers interconnecting the first IC die and the second IC die through a hybrid bond comprising a plurality of directly bonded metal contact pads and directly bonded non-conductive regions,

wherein the processor core is electrically connected to the cache through at least one of the plurality of directly bonded metal contact pads disposed within an area defined by overlapping circuit blocks on the first and second IC dies.

22. The 3D processor circuit of claim 21 , wherein the cache is a first cache and the first IC die further comprises a second cache.

23. The 3D processor circuit of claim 21 , wherein adjacent metal contact pads have a pitch between 0.5 μm and 15 μm.

24. The 3D processor circuit of claim 21 , wherein the first IC die and the second IC die are face-to-back mounted.

25. The 3D processor circuit of claim 21 , wherein:

at least one of the first IC die and the second IC die comprises through silicon vias (TSVs); and

a signal path communicatively coupling the processor core and the cache further comprises at least one of the TSVs.

26. The 3D processor circuit of claim 21 , wherein the overlapping circuit blocks comprise a first circuit block comprising at least a portion of the processor core and a second circuit block comprising at least a portion of the cache.

Assignments (4)

Continuity (19)

References Cited (278)