IP Library Granted Patent US 12,162,114
Granted Patent B2
US 12,162,114 · App. 17/488,859 · Granted Dec 10, 2024

Polishing pad, manufacturing method thereof and preparing method of semiconductor device using the same

Inventors: Jong Wook Yun (Seoul, KR); Jae In Ahn (Gyeonggi-do, KR); Eun Sun Joeng (Gyeonggi-do, KR); Hye Young Heo (Gyeonggi-do, KR); Jang Won Seo (Seoul, KR)
Assignee: SK ENPULSE CO., LTD.
B24B29/00C08J9/32H01L21/30625C08J2203/22C08J2205/044C08J2207/00C08J2375/04
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Quick Facts
Patent No.
US 12,162,114
App. No.
17/488,859
Granted
Dec 10, 2024
Kind
B2
Abstract

The present disclosure relates to a polishing pad, a method of manufacturing the polishing pad, and a method of manufacturing a semiconductor device using the same. In the polishing pad, an unexpanded solid-phase blowing agent is included in a polishing composition when a polishing layer is manufactured, and the unexpanded solid-phase blowing agent is expanded during a curing process to form a plurality of uniform pores in the polishing layer, such that defects occurring on a surface of the semiconductor substrate may be prevented. In addition, the present disclosure may provide a method of manufacturing a semiconductor device to which the polishing pad is applied.

Claims (220)

1. A polishing pad, comprising a polishing layer, wherein the polishing layer includes a plurality of pores, and

the pores have a value of 0.5 to 1 according to the following Equation 1 or 2,

wherein the pores formed in the polishing layer have a D50 of 15 to 65 μm:

D

10

D

50

[

Equation

1

]

D

50

D

9

0

[

Equation

2

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores on 50% cumulative volume distribution, and

D90 is a diameter of pores on 90% cumulative volume distribution.

2. The polishing pad of claim 1 , wherein the pores have a standard deviation of 2 to 9 of measured values for D10 to D90.

3. The polishing pad of claim 1 , wherein the polishing layer has a real contact area of 0.02 to 0.05 mm 2 with a semiconductor substrate.

4. The polishing pad of claim 1 , wherein the pores have a value of 0.5 to 1.5 according to the following Equation 3:

(

D

90

-

D

50

)

(

D

50

-

D

10

)

[

Equation

3

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores in 50% cumulative volume distribution, and

D90 is a diameter of pores in 90% cumulative volume distribution.

5. The polishing pad of claim 1 , wherein the polishing layer includes a shell derived from an unexpanded solid-phase blowing agent.

6. The polishing pad of claim 5 , wherein the shell is one or more selected from the group consisting of a vinylidene chloride-based copolymer, an acrylonitrile-based copolymer, a methacrylonitrile-based copolymer and an acryl-based copolymer.

7. A method of manufacturing a polishing pad, the method comprising:

i) preparing a prepolymer composition;

ii) preparing a composition for manufacturing a polishing layer, containing the prepolymer composition, a blowing agent and a curing agent; and

iii) curing the composition for manufacturing a polishing layer to prepare a polishing layer,

wherein the polishing layer includes a plurality of pores, and

the pores have a value of 0.5 to 1 according to the following Equation 1 or 2,

wherein the pores formed in the polishing layer have a D50 of 15 to 65 μm:

D

10

D

50

[

Equation

1

]

D

50

D

90

[

Equation

2

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores on 50% cumulative volume distribution, and

D90 is a diameter of pores on 90% cumulative volume distribution.

8. The method of claim 7 , wherein the pores have a value of 0.5 to 1.5 according to the following Equation 3:

(

D

90

-

D

50

)

(

D

50

-

D

10

)

[

Equation

3

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores in 50% cumulative volume distribution, and

D90 is a diameter of pores in 90% cumulative volume distribution.

9. The method of claim 7 , wherein the blowing agent includes an unexpanded solid-phase blowing agent.

10. The method of claim 9 , wherein the unexpanded solid-phase blowing agent is expanded by the curing of the step iii) to form a plurality of pores with a uniform size.

11. The method of claim 7 , wherein the polishing layer includes a shell derived from an unexpanded solid-phase blowing agent.

12. The method of claim 7 , wherein

in step iii), the composition for manufacturing a polishing layer is injected into a preheated mold and cured, and

the preheating temperature of the mold is 50 to 150° C.

13. The method of claim 7 , wherein the pores have a standard deviation of 2 to 9 of measured values for D10 to D90.

14. A method of manufacturing a semiconductor device, the method comprising:

1) Providing a polishing pad including a polishing layer; and

2) Polishing the semiconductor substrate while rotating the semiconductor substrate and the polishing layer relative to each other so that a polished surface of the semiconductor substrate is in contact with the polishing surface of the polishing layer,

wherein the polishing layer includes a plurality of pores, and

the pores have a value of 0.5 to 1 according to the following Equation 1 or 2,

wherein the pores formed in the polishing layer have a D50 of 15 to 65 μm:

D

10

D

50

[

Equation

1

]

D

50

D

90

[

Equation

2

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores on 50% cumulative volume distribution, and

D90 is a diameter of pores on 90% cumulative volume distribution.

15. The method of claim 14 , wherein the pores have a value of 0.5 to 1.5 according to the following Equation 3:

(

D

90

-

D

50

)

(

D

50

-

D

10

)

[

Equation

3

]

wherein

D10 is a diameter of pores in 10% cumulative volume distribution,

D50 is a diameter of pores in 50% cumulative volume distribution, and

D90 is a diameter of pores in 90% cumulative volume distribution.

16. The method of claim 14 , wherein the polishing layer has a real contact area of 0.02 to 0.05 mm 2 with a semiconductor substrate.

17. The method of claim 14 , wherein the pores have a standard deviation of 2 to 9 of measured values for D10 to D90.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2025
From: SK ENPULSE CO., LTD.
To: ENPULSE CO., LTD.
Reel/Frame 071308/0411 →
CHANGE OF NAME Recorded May 3, 2023
From: SKC SOLMICS CO., LTD.
To: SK ENPULSE CO., LTD.
Reel/Frame 063530/0303 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2021
From: YUN, JONG WOOK; AHN, JAE IN; JOENG, EUN SUN; HEO, HYE YOUNG; SEO, JANG WON
To: SKC SOLMICS CO., LTD.
Reel/Frame 057641/0035 →
Priority Claims (2)
KR 10-2020-0126794 · Sep 29, 2020 · national
KR 10-2020-0126799 · Sep 29, 2020 · national
Continuity (1)
Related Publication 20220097201A1 · Mar 31, 2022