Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices
Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.
1. A processor comprising:
a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution;
temperature-measurement circuitry configured to monitor an on-chip temperature of the processor; and
control logic configured to:
determine whether the processor is active or idle;
determine whether the on-chip temperature of the processor exceeds a first threshold;
based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and
selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second threshold, the second threshold being greater than the first threshold.
2. The processor of claim 1 , wherein the processor comprises a graphics processing unit.
3. The processor of claim 1 , wherein the temperature-measurement circuitry is configured to monitor the on-chip temperature of the processor at least in part by:
obtaining one or more temperature readings made at one or more junction points of a package interface of the processor; and
calculating the on-chip temperature of the processor based on the one or more obtained temperature readings.
4. The processor of claim 1 , wherein the temperature-measurement circuitry is configured to monitor the on-chip temperature of the processor at least in part by directly measuring the on-chip temperature of the processor.
5. The processor of claim 1 , wherein the control logic being configured to disable the one or more idle-mode power-saving features of the processor comprises the control logic being configured to disable one or more of dynamic power gating of idle blocks of the processor, dynamic clock gating of sequential elements on the processor, dynamic clock gating of idle logic units on the processor, and dynamic gating of clock trees on the processor.
6. The processor of claim 1 , wherein selectively adjusting the one or more operating parameters of the processor comprises selectively adjusting one or both of an operating frequency of a clock signal of the processor and an operating frequency of a clock tree of the processor.
7. The processor of claim 1 , wherein selectively adjusting the one or more operating parameters of the processor comprises selectively adjusting an input voltage to at least one hardware component of the processor.
8. At least one non-transitory computer-readable storage medium containing instructions that, when executed by at least one hardware processor, cause the hardware processor to perform operations comprising:
monitoring an on-chip temperature of the processor;
based on determining that the processor is idle and that the on-chip temperature of the processor exceeds a first threshold, disabling one or more idle-mode power-saving features of the processor; and
selectively adjusting one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second threshold, the second threshold being greater than the first threshold.
9. The at least one non-transitory computer-readable storage medium of claim 8 , wherein the processor comprises a graphics processing unit.
10. The at least one non-transitory computer-readable storage medium of claim 8 , wherein monitoring the on-chip temperature of the processor comprises:
obtaining one or more temperature readings made at one or more junction points of a package interface of the processor; and
calculating the on-chip temperature of the processor based on the one or more obtained temperature readings.
11. The at least one non-transitory computer-readable storage medium of claim 8 , wherein monitoring the on-chip temperature of the processor comprises directly measuring the on-chip temperature of the processor.
12. The at least one non-transitory computer-readable storage medium of claim 8 , wherein disabling the one or more idle-mode power-saving features of the processor comprises disabling one or more of dynamic power gating of idle blocks of the processor, dynamic clock gating of sequential elements on the processor, dynamic clock gating of idle logic units on the processor, and dynamic gating of clock trees on the processor.
13. The at least one non-transitory computer-readable storage medium of claim 8 , wherein selectively adjusting the one or more operating parameters of the processor comprises selectively adjusting one or both of an operating frequency of a clock signal of the processor and an operating frequency of a clock tree of the processor.
14. The at least one non-transitory computer-readable storage medium of claim 8 , wherein selectively adjusting the one or more operating parameters of the processor comprises selectively adjusting an input voltage to at least one hardware component of the processor.
15. A method performed by a processor, the method comprising:
monitoring an on-chip temperature of the processor;
based on determining that the processor is idle and that the on-chip temperature of the processor exceeds a first threshold, disabling one or more idle-mode power-saving features of the processor; and
selectively adjusting one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second threshold, the second threshold being greater than the first threshold.
16. The method of claim 15 , wherein the processor comprises a graphics processing unit.
17. The method of claim 15 , wherein monitoring the on-chip temperature of the processor comprises:
obtaining one or more temperature readings made at one or more junction points of a package interface of the processor; and
calculating the on-chip temperature of the processor based on the one or more obtained temperature readings.
18. The method of claim 15 , wherein monitoring the on-chip temperature of the processor comprises directly measuring the on-chip temperature of the processor.
19. The method of claim 15 , wherein disabling the one or more idle-mode power-saving features of the processor comprises disabling one or more of dynamic power gating of idle blocks of the processor, dynamic clock gating of sequential elements on the processor, dynamic clock gating of idle logic units on the processor, and dynamic gating of clock trees on the processor.
20. The method of claim 15 , wherein selectively adjusting the one or more operating parameters of the processor comprises selectively adjusting one or both of an operating frequency of a clock signal of the processor and an operating frequency of a clock tree of the processor.