Area efficient traffic generator
A packet and inspection system for monitoring the performance of one or more flows on a packet network comprises a processor and memory coupled to each other and to a network bus. The memory stores instructions to be executed by the processor and data to be modified by the execution of the instructions. A processor-controlled arbiter is coupled with the processor and the network bus, and upon reception of a packet on the bus or prior to transmission of a packet on the bus for one of said flows, the arbiter requests execution by the processor of selected instructions stored in the memory by providing the processor with the address of the selected instructions in the memory. The memory provides the processor with data associated with the selected instructions, and the processor modifies the data upon execution of the selected instructions.
1. A system to monitor performance of one or more flows on a packet network, said system comprising:
a memory comprising a plurality of operating codes and a plurality of associated data;
a centralized arbiter accessing said memory to trigger a processor to execute one or more functions pre-programmed in the processor corresponding with one or more of said plurality of operating codes and one or more of said plurality of associated data;
wherein said one or more functions generate a test packet to be inserted in one of said one or more flows; and
wherein said one or more functions are managed via an addition operation and a subtraction operation in parallel.
2. The system of claim 1 in which said processor is implemented as a field programmable gate array (FPGA).
3. The system of claim 1 further comprising a shaping bucket debited to control an amount of test packets generated.
4. A method to monitor performance at a network device coupled to one or more flows in a packet network, said method comprising:
storing, in a memory, a plurality of operating codes and a plurality of associated data;
arbitrating access to said memory and executing, by a processor coupled to said memory, one or more functions pre-programmed in the processor corresponding with one or more of said plurality of operating codes and one or more of said plurality of associated data; and
generating a test packet to be inserted in one of said one or more flows; and
wherein said one or more functions are managed via an addition operation and a subtraction operation in parallel.
5. The method of claim 4 in which said processor is implemented as a field programmable gate array (FPGA).
6. The method of claim 4 further comprising debiting a shaping bucket to control an amount of test packets generated.
7. The system of claim 1 , wherein a copy function is performed by forcing a subtraction by zero.
8. The method of claim 4 , wherein a copy function is performed by forcing a subtraction by zero.
9. A non-transitory computer-readable medium comprising instructions that when executed by a processor, configure the processor to:
store, in a memory, a plurality of operating codes and a plurality of associated data;
arbitrate access to said memory and executing, by a processor coupled to said memory, one or more functions pre-programmed in the processor corresponding with one or more of said plurality of operating codes and one or more of said plurality of associated data;
generate a test packet to be inserted in one of one or more flows in a packet network; and
wherein said one or more functions are managed via an addition operation and a subtraction operation in parallel.