2D-channel transistor structure with asymmetric substrate contacts
Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.
1. A semiconductor structure comprising:
a dielectric layer on a semiconductor substrate;
a conductive feature embedded in the dielectric layer;
a channel layer of 2-dimensional (2D) material or carbon nanotube (CNT) disposed on the dielectric layer;
a gate stack disposed on the channel layer;
a via feature disposed on the conductive feature and underlying the channel layer;
a source contact disposed on one side of the gate stack and on the channel layer such that the channel layer is sandwiched between the source contact and the via feature; and
a drain contact disposed on an opposite side of the gate stack, wherein the source contact, the channel layer and the via feature electrically connects to the conductive feature, and wherein the drain contact extends to the channel layer and is isolated from the conductive feature by the dielectric layer.
2. The semiconductor structure of claim 1 , wherein the channel layer includes multiple channel members and wherein the source contact contacts each of the multiple channel members.
3. The semiconductor structure of claim 2 , wherein
the multiple channel members include a spacing S among adjacent two of the multiple channel members along the second direction;
each of the multiple channel members includes a dimension D;
a ratio of (S+D)/D ranges between 1.3 and 3; and
a number of the multiple channel members is equal to or greater than 3.
4. The semiconductor structure of claim 1 , wherein
the dielectric layer includes a first dielectric film and a second dielectric film sandwiched the conductive feature; and
the source contact is isolated from the semiconductor substrate by the first dielectric film.
5. The semiconductor structure of claim 1 , wherein the via feature source contact extends into the conductive feature.
6. The semiconductor structure of claim 1 , wherein the source contact and the drain contact include coplanar top surfaces.
7. The semiconductor structure of claim 1 , wherein
the gate stack spans between a first edge and a second edge;
the first edge is adjacent to the source contact and the second edge is adjacent to the drain contact; and
the conductive feature laterally extends to the second edge of the gate stack.
8. The semiconductor structure of claim 7 , wherein the conductive feature includes an edge being aligned with the second edge of the gate stack.
9. The semiconductor structure of claim 1 , wherein
the channel layer longitudinally extends along a first direction;
the gate stack longitudinally extends along a second direction that substantially orthogonal to the first direction;
the source contact extends a first width along the first direction;
the via feature extends a second width along the first direction; and
the second width is less than the first width.
10. The semiconductor structure of claim 1 , wherein each of the conductive feature, the source contact, and the drain contact includes at least one metal selected from tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta) and aluminum (Al).
11. The semiconductor structure of claim 1 , further comprising:
an etch stop layer of a first dielectric material disposed on the channel layer;
an interlayer dielectric layer of a second dielectric material disposed on the etch stop layer; and
a self-aligned cap layer of a third dielectric material formed on a top of the gate stack and spanning between two edges contacting sidewalls of the etch stop layer, wherein the first, second and third dielectric materials are different from each in composition.
12. The semiconductor structure of claim 11 , wherein
the first dielectric material includes one of silicon oxide and silicon nitride;
the second dielectric material includes one of undoped silica glass (USG), phosphosilicate glass (PSG), boron-doped phosphosilicate glass (BPSG), borosilicate glass (BSG);
the first dielectric material includes one of silicon nitride, aluminum oxide, silicon carbide, hafnium oxide, zirconium oxide; and
the self-aligned cap layer, the etch stop layer and the interlayer dielectric layer include a coplanar top surface.
13. A semiconductor structure comprising:
a first dielectric film on a semiconductor substrate;
a metal feature embedded in the first dielectric film;
a second dielectric film on the first dielectric film and the metal feature;
a via feature embedded in the second dielectric film and landing on the metal feature;
a channel layer of 2-dimensional (2D) material or carbon nanotube (CNT) disposed on the second dielectric film;
a gate stack disposed on the channel layer; and
a source contact and a drain contact disposed on both sides of the gate stack and landing on the channel layer, wherein
the channel layer is inserted between the source contact and the via feature,
the source contact overlaps with the via feature and the metal feature in a top view,
the drain contact is distanced away from the via feature in the top view, and
the source contact is isolated from the semiconductor substrate by the first dielectric film.
14. The semiconductor structure of claim 13 , wherein
the source contact includes a top surface and a bottom surface; and
the drain contact includes a top surface being coplanar with the top surface of the source contact and a bottom surface being coplanar with the bottom surface of the source contact.
15. The semiconductor structure of claim 13 , wherein
the channel layer is longitudinally oriented along a first direction;
the gate stack is longitudinally oriented along a second direction being orthogonal to the first direction;
the source contact spans a first dimension along the first direction;
the via feature spans a second dimension along the first direction;
the metal feature spans a third dimension along the first direction;
the second dimension is greater than the first dimension; and
the third dimension is greater than each of the first and second dimensions.
16. The semiconductor structure of claim 15 , wherein
the gate stack spans between a first edge and a second edge along the first direction; and
the metal feature laterally extends from the via feature to the first edge and further extends to the second edge of the gate stack.
17. The semiconductor structure of claim 16 , further comprising:
an etch stop layer of a first dielectric material disposed on the channel layer;
an interlayer dielectric layer of a second dielectric material disposed on the etch stop layer; and
a self-aligned cap layer formed of a third dielectric material on a top of the gate stack and spanning between two edges contacting sidewalls of the etch stop layer, wherein the first, second and third dielectric materials are different from each in composition.
18. The semiconductor structure of claim 13 , wherein
the channel layer includes multiple channel members; and
the source contact contacts each of the multiple channel members.
19. A semiconductor structure comprising:
a first dielectric layer on a semiconductor substrate;
a conductive feature on the first dielectric layer;
a second dielectric layer on the conductive feature such that the conductive feature is sandwiched between the first and second dielectric layer;
a via feature embedded in the second dielectric layer;
a channel layer of 2-dimensional (2D) material or carbon nanotube (CNT) disposed on the second dielectric layer;
a gate stack disposed on the channel layer; and
a source contact and a drain contact disposed on both sides of the gate stack, wherein the channel layer is inserted between the via feature and the source contact, wherein the conductive feature is electrically connected to the conductive feature through the channel layer and the via feature, and wherein the drain contact extends to the channel layer and is isolated from the conductive feature by the second dielectric layer.
20. The semiconductor structure of claim 19 , wherein
the channel layer includes multiple channel members; and
the source contact contacts each of the multiple channel members.