IP Library Granted Patent US 10,163,691
Granted Patent B2
US 10,163,691 · App. 15/707,657 · Granted Dec 25, 2018

Low-K dielectric interconnect systems

Inventors: Po-Cheng Shih (Hsin Chu, TW); Chia Cheng Chou (Keelung, TW); Chung-Chi Ko (Nantou, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/76825H01L21/3105H01L21/31144H01L21/76802
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Quick Facts
Patent No.
US 10,163,691
App. No.
15/707,657
Granted
Dec 25, 2018
Kind
B2
Abstract

A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.

Claims (52)

1. A method of fabricating a semiconductor device, comprising:

forming a low-k dielectric layer;

depositing a cap layer over the low-k dielectric layer, the depositing the cap layer includes:

forming a bottom cap layer over the low-k dielectric layer; and

forming a top cap layer of the cap layer over the bottom cap layer, wherein the top cap layer includes a metal;

etching the low-k dielectric layer to form a first trench and a second trench using the cap layer as an etching mask.

2. The method of claim 1 , wherein the bottom cap layer includes silicon oxycarbide.

3. The method of claim 1 , further comprising:

prior to the etching the low-k dielectric layer, performing a treatment process to the cap layer.

4. The method of claim 1 , further comprising:

prior to the etching the low-k dielectric layer, performing a treatment process to the cap layer;

wherein the cap layer induces a first stress on the low-k dielectric layer prior to the performing the treatment process,

wherein the cap layer induces a second stress different from the first stress on the low-k dielectric layer after the performing the treatment process, and

wherein an absolute value of the second stress is less than about 50% of an absolute value of the first stress.

5. The method of claim 4 , further comprising:

prior to the performing the depositing the cap layer, performing a second treatment process to the low-k dielectric layer to change a dielectric constant of the low-k dielectric layer.

6. The method of claim 5 , wherein during the performing the treatment process, the dielectric constant of the low-k dielectric layer remains substantially the same.

7. The method of claim 6 , further comprising:

after the etching the low-k dielectric layer to form the first and second trenches, irradiating sidewalls and bottoms of the first and second trenches with a third radiation to change the dielectric constant of the low-k dielectric layer.

8. A method, comprising:

providing a layout of a connective layer including a first pattern having a first width in a first direction and a second pattern disposed at a distance from the first pattern in the first direction;

forming a low-k dielectric layer having a height over a substrate;

depositing a cap layer over the low-k dielectric layer;

irradiating a top surface of the cap layer with a first radiation;

patterning the cap layer to form a first opening associated with the first pattern and a second opening associated with the second pattern; and

performing an etching process to transfer the first opening to a first trench in the low-k dielectric layer and transfer the second opening to a second trench in the low-k dielectric layer.

9. The method of claim 8 ,

wherein a ratio between the height and the distance is greater than a pre-defined height-to-width aspect ratio threshold; and

wherein the pre-defined height-to-width aspect ratio threshold is greater than about 5:1.

10. The method of claim 9 , wherein after the performing the etching process, the first trench has a second width at a top surface of the low-k dielectric layer, and

wherein the first width and the second width are substantially the same.

11. The method of claim 10 , wherein a difference between the first width and the second width is less than about 10% of the first width.

12. The method of claim 11 , further comprising:

prior to the depositing the cap layer, irradiating the low-k dielectric layer with a second radiation.

13. The method of claim 12 , wherein the second radiation has a second wavelength different from a first wavelength of the first radiation.

14. The method of claim 13 , further comprising:

after the etching the low-k dielectric layer to form the first trench and the second trench, irradiating sidewalls and bottoms of the first trench and the second trench with a third radiation to change a dielectric constant of the low-k dielectric layer.

15. The method of claim 14 , wherein the third radiation has a third wavelength different from the first wavelength of the first radiation.

16. A method, comprising:

forming a low-k dielectric layer over a substrate;

forming a lower cap layer over the low-k dielectric layer;

forming an upper cap layer over the lower cap layer; and

performing a first treatment process to the cap layer,

wherein the lower cap layer has a first hardness prior to the first treatment process and a second hardness greater than the first hardness after the first treatment process; and

wherein during the first treatment process, a dielectric constant of the low-k dielectric layer remains substantially the same; and

etching the low-k dielectric layer to form a plurality of trenches using the cap layer as an etching mask.

17. The method of claim 16 , further comprising:

prior to the performing the depositing the cap layer, performing a second treatment process to the low-k dielectric layer to change the dielectric constant of the low-k dielectric layer.

18. The method of claim 16 , wherein the performing the first treatment process includes:

irradiating an ultraviolet (UV) radiation on the cap layer.

19. The method of claim 16 , wherein the lower cap layer includes silicon oxycarbide.

20. The method of claim 16 , wherein the upper cap layer includes a metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2017
From: SHIH, PO-CHENG; CHOU, CHIA CHENG; KO, CHUNG-CHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 043840/0648 →
Continuity (2)
Continuation 15168596 · May 31, 2016
Related Publication 20180005882A1 · Jan 4, 2018
Cited By (11)
US 12,205,896 US 12,300,496 US 12,406,877 US 12,433,003 US 12,444,646 US 12,444,676 US 12,525,485 US 12,550,694 US 12,568,670 US 12,733,241 US 12,733,469