Gate contact structure
Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.
1 . A method, comprising:
providing a semiconductor structure that includes a gate structure and a source/drain contact over an active region, a selectivity metal layer over the gate structure, and a self-aligned capping (SAC) layer over the selectivity metal layer;
depositing an etch stop layer (ESL) and a dielectric layer over the SAC layer;
after the depositing of the ESL and the dielectric layer, forming a gate contact opening through the dielectric layer, the ESL, and the SAC to expose the selectivity metal layer;
depositing a first glue layer over the gate contact opening to contact the selectivity metal layer over the gate structure;
depositing a first metal fill layer over the first glue layer;
etching back the first metal fill layer and the first glue layer;
after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact;
depositing a second glue layer over the first metal fill layer in the gate contact opening and the source/drain contact via opening;
depositing a second metal fill layer over the second glue layer; and
after the depositing of the second metal fill layer, planarizing the semiconductor structure,
wherein the etching back comprises a dry etch process that uses oxygen, hydrogen, nitrous oxide, nitrogen, a fluorine-containing gas, or a chlorine-containing gas,
wherein the dry etch process comprises a direct current (DC) bias between about 100 V and about 800 V,
wherein the dry etch process comprises a radio frequency (RF) power between about 100 W and about 300 W and a temperature between about 20° C. and about 90° C.
2 . The method of claim 1 , wherein the depositing of the first metal fill layer comprises depositing the first metal fill layer until a top surface of the first metal fill layer is higher than a top surface of the SAC layer.
3 . The method of claim 1 , wherein, after the depositing of the first metal fill layer, the gate contact opening is not completely filled.
4 . The method of claim 1 , wherein the first glue layer and the second glue layer comprise cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.
5 . The method of claim 1 , wherein the etching back comprises etching the first metal fill layer until a top surface of the first metal fill layer is substantially coplanar with a top surface of the SAC layer.
6 . The method of claim 1 , wherein, after the depositing of the second glue layer, the second glue layer is in direct contact with a top surface of the first glue layer, a top surface of the first metal fill layer, the ESL, and the dielectric layer.
7 . The method of claim 1 , wherein, after the depositing of the second metal fill layer, the second metal fill layer is spaced apart from a top surface of the first glue layer, a top surface of the first metal fill layer, the ESL, and the dielectric layer by the second glue layer.
8 . The method of claim 1 ,
wherein the gate structure extends lengthwise along a first direction,
wherein the gate structure is disposed between a first gate spacer and a second gate spacer along a second direction different from the first direction,
wherein a portion of the SAC layer is disposed between the first gate spacer and the second gate spacer along the second direction.
9 . The method of claim 1 , wherein, after the depositing of the first metal fill layer, the gate contact opening is not completely filled.
10 . A method, comprising:
providing a semiconductor structure that includes a gate structure and a source/drain contact over an active region, a gate spacer disposed between the gate structure and the source/drain contact, a selectivity metal layer over the gate structure, and a self-aligned capping (SAC) layer over the selectivity metal layer and the gate spacer;
depositing an etch stop layer (ESL) and a dielectric layer over the SAC layer;
forming a gate contact opening through the dielectric layer, the ESL, and the SAC to expose the selectivity metal layer;
depositing a first glue layer over the gate contact opening;
depositing a first metal fill layer over the first glue layer without completely filling the gate contact opening;
etching back the first metal fill layer and the first glue layer until a top surface of the first metal fill layer is lower than a top surface of the ESL but is higher than a top surface of the gate spacer;
after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact;
depositing a second glue layer over the first metal fill layer in the gate contact opening and the source/drain contact via opening;
depositing a second metal fill layer over the second glue layer; and
after the depositing of the second metal fill layer, planarizing the semiconductor structure,
wherein the etching back comprises a dry etch process that uses oxygen, hydrogen, nitrous oxide, nitrogen, a fluorine-containing gas, or a chlorine-containing gas,
wherein the dry etch process comprises a direct current (DC) bias between about 100 V and about 800 V,
wherein the dry etch process comprises a radio frequency (RF) power between about 100 W and about 300 W and a temperature between about 20° C. and about 90° C.
11 . The method of claim 10 ,
wherein the forming of the gate contact opening is performed after the depositing of the ESL and the dielectric layer, and
wherein, after the depositing of the first metal fill layer, the gate contact opening is not completely filled.
12 . The method of claim 10 , wherein, after the depositing of the second glue layer, the second glue layer is in direct contact with a top surface of the first glue layer, a top surface of the first metal fill layer, the ESL, and the dielectric layer.
13 . The method of claim 10 , wherein, after the depositing of the second metal fill layer, the second metal fill layer is spaced apart from a top surface of the first glue layer, a top surface of the first metal fill layer, the ESL, and the dielectric layer by the second glue layer.
14 . The method of claim 10 ,
wherein a thickness of the first glue layer is between about 1 Å and about 30 Å,
wherein a thickness of the second glue layer is between about 1 Å and about 30 Å.
15 . The method of claim 10 , wherein the first glue layer and the second glue layer comprise cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof.
16 . A method, comprising:
providing a semiconductor structure that includes a gate structure and a source/drain contact over an active region, a selectivity metal layer over the gate structure, and a self-aligned capping (SAC) layer over the selectivity metal layer;
depositing an etch stop layer (ESL) and a dielectric layer over the SAC layer;
after the depositing of the ESL and the dielectric layer, forming a gate contact opening through the dielectric layer, the ESL, and the SAC to expose the selectivity metal layer over the gate structure;
depositing a first metal fill layer over the gate contact opening without completely filling the gate contact opening;
etching back the first metal fill layer;
after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact;
depositing a second metal fill layer over the first metal fill layer in the gate contact opening and the source/drain contact via opening; and
after the depositing of the second metal fill layer, planarizing the semiconductor structure,
wherein the etching back comprises use of a fluorine-containing gas, chlorine, hydrogen, oxygen, nitrous oxide, or nitrogen,
wherein the etching back comprises:
a bias between about 100 volts and about 800 volts, and
a temperature between about 20° C. and about 90°.
17 . The method of claim 16 , further comprising:
before depositing the first metal fill layer, depositing a first glue layer over the gate contact opening.
18 . The method of claim 16 , further comprising:
before depositing the second metal fill layer, depositing a second glue layer over the first metal fill layer and the source/drain contact via opening.
19 . The method of claim 16 , wherein a composition of the selectivity metal layer is different from a composition of the source/drain contact.
20 . The method of claim 16 , wherein the etching back comprises etching the first metal fill layer until a top surface of the first metal fill layer is substantially coplanar with a top surface of the SAC layer.