Power delivery through capacitor-dies in a multi-layered microelectronic assembly

1. A microelectronic assembly, comprising:

an integrated circuit (IC) die in a first layer; and

a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being coupled by conductive pathways in the IC die,

wherein:

the first layer and the second layer are coupled by interconnects, and

the IC die comprises capacitors and voltage regulator circuitry.

2. The microelectronic assembly of claim 1 , wherein:

the first layer comprises a dielectric material at least partially surrounding the IC die, and

the first layer further comprises through-dielectric vias (TDVs) in the dielectric material.

3. The microelectronic assembly of claim 2 , wherein the dielectric material comprises a compound of silicon and at least one of oxygen, carbon, or nitrogen.

4. The microelectronic assembly of claim 1 , wherein:

a first sub-set of the capacitors is to operate at a first voltage,

a second sub-set of the capacitors is to operate at a second voltage, and

the first voltage is higher than the second voltage.

5. The microelectronic assembly of claim 4 , wherein:

the first sub-set of capacitors is coupled to a first voltage regulator, and

the second sub-set of the capacitors is coupled to a second voltage regulator.

6. The microelectronic assembly of claim 1 , wherein the capacitors comprise metal-insulator-metal (MIM) capacitors embedded in a metallization stack of the IC die.

7. The microelectronic assembly of claim 1 , wherein the capacitors comprise corrugated capacitors embedded in a metallization stack of the IC die.

8. The microelectronic assembly of claim 1 , wherein the capacitors comprise deep-trench capacitors (DTC) embedded in a substrate of the IC die.

9. The microelectronic assembly of claim 1 , wherein the interconnects have a pitch of less than 10 micrometers between adjacent interconnects.

10. An IC package, comprising:

a package substrate in a first layer;

a first IC die in a second layer;

a second IC die and a third IC die in a third layer; and

a fourth IC die in a fourth layer,

wherein:

the second layer is between the first layer and the third layer,

the fourth layer is between the first layer and the second layer,

the first IC die includes capacitors,

the fourth IC die includes other capacitors,

conductive pathways in the first IC die couples the second IC die and the third IC die, and

the second layer and the third layer are coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects.

11. The IC package of claim 10 , wherein the capacitors are in at least one of a metallization stack and a substrate of the first IC die.

12. The IC package of claim 11 , wherein:

the metallization stack of the first IC die is proximate to the second IC die and the third IC die, and

vias in the metallization stack of the first IC die are to couple the capacitors to the second IC die and the third IC die.

13. The IC package of claim 11 , wherein:

the metallization stack of the first IC die is proximate to the package substrate, and

through-substrate vias (TSVs) in the first IC die and vias in the metallization stack of the first IC die are to couple the capacitors to the second IC die and the third IC die.

14. An IC structure, comprising:

a metallization stack comprising a plurality of layers of conductive traces separated by a first dielectric material, and further comprising conductive vias in the first dielectric material;

an inorganic substrate proximate to the metallization stack;

a plurality of capacitors; and

interconnects proximate to the metallization stack,

wherein:

the IC structure is coupled by the interconnects in a multi-layered structure comprising IC dies distributed in two or more layers, and

at least one of the IC dies is surrounded by a second dielectric material and through-dielectric vias (TDVs) in the second dielectric material.

15. The IC structure of claim 14 , wherein at least one of the capacitors comprises a metal-insulator-metal (MIM) capacitor.

16. The IC structure of claim 15 , wherein:

a first portion of the metallization stack comprises first conductive traces having a first pitch,

a second portion of the metallization stack comprises second conductive traces having a second pitch,

the second pitch is larger than the first pitch, and

the MIM capacitor is in the second portion.

17. The IC structure of claim 14 , wherein:

a first sub-set of the capacitors is to operate at a first voltage,

the first sub-set of the capacitors is proximate to a first side of the IC structure,

a second sub-set of the capacitors is to operate at a second voltage,

the second sub-set of the capacitors is proximate to a second side of the IC structure opposite to the first side, and

the first voltage is different from the second voltage.

18. The IC structure of claim 14 , wherein:

a voltage regulation circuitry on one or more IC dies in the multi-layered structure is coupled to one or more of the plurality of capacitors, and

the voltage regulation circuitry comprises at least one of a low drop-out regulator, a switched capacitor regulator and a buck regulator.

19. The IC structure of claim 18 , wherein:

the voltage regulation circuitry comprises at least two stages,

a first stage is to convert from a first voltage to a second voltage,

the first stage is in a first IC die in the multi-layered structure,

a second stage is to convert from the second voltage to a third voltage,

the second stage is in a second IC die in the multi-layered structure, and

the first IC die and the second IC die are coupled to the plurality of capacitors in the IC structure.

20. The IC structure of claim 14 , wherein the interconnects have a pitch of less than 10 micrometers.