IP Library › Granted Patent US 12,315,863
Granted Patent B2
US 12,315,863 · App. 17/533,575 · Granted May 27, 2025

Contact structures in semiconductor devices

Inventors: Mrunal Abhijith Khaderbad (Hsinchu, TW); Wei-Yen Woon (Hsinchu, TW); Cheng-Ming Lin (Kaohsiung, TW); Han-Yu Lin (Hsinchu, TW); Szu-Hua Chen (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/401H01L21/28518H01L21/28525H01L21/28568H01L29/41733H01L29/41791H01L29/42392H01L29/456
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Quick Facts
Patent No.
US 12,315,863
App. No.
17/533,575
Granted
May 27, 2025
Kind
B2
Abstract

The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

Claims (55)

1. A method, comprising:

forming a fin structure on a substrate;

forming a gate structure on the fin structure;

forming a source/drain (S/D) region on the fin structure not covered by the gate structure; and

forming a contact structure on the S/D region, wherein forming the contact structure comprises:

forming a liner layer on the S/D region;

forming, after etching a portion of the liner layer from a top surface of the S/D region, a transition metal chalcogenide (TMC) layer comprising a bottom surface in contact with the top surface of the S/D region and a first sidewall in contact with a first portion of the liner layer; and

forming a contact plug comprising a bottom surface in contact with a top surface of the TMC layer and a second sidewall in contact with a second portion of the liner layer.

2. The method of claim 1 , wherein a ratio between a thickness of the TMC layer and a length of the TMC layer along the fin structure is between about 0.017:1 and about 0.3:1.

3. The method of claim 1 , wherein forming the TMC layer comprises:

depositing a layer of chalcogen material on the S/D region at a temperature between about 300° C. and about 800° C. with a plasma process or between about 500° C. and about 1100° C. without a plasma process; and

depositing a layer of transition metal on the layer of chalcogen material at a temperature between about 300° C. and about 800° C. with a plasma process or between about 500° C. and about 1100° C. without a plasma process.

4. The method of claim 1 , wherein forming the TMC layer comprises:

depositing a layer of chalcogen material on the S/D region; and

depositing a layer of transition metal on the layer of chalcogen material.

5. The method of claim 1 , wherein forming the TMC layer comprises:

forming a contact opening on the S/D region;

depositing a layer of chalcogen material on the S/D region without depositing on sidewalls of the contact opening; and

depositing a layer of transition metal on the layer of chalcogen material without depositing on sidewalls of the contact opening.

6. The method of claim 1 , wherein forming the TMC layer comprises selectively depositing a layer of sulfur, selenium, or tellurium on the S/D region.

7. The method of claim 1 , wherein forming the TMC layer comprises selectively forming a layer of sulfide, selenide, or telluride on the S/D region.

8. The method of claim 1 , wherein a ratio between a thickness of the TMC layer and a thickness of the liner layer is between about 1:1 and about 2:1.

9. The method of claim 1 , wherein forming the liner layer comprises forming a layer of transition metal chalcogenide material.

10. The method of claim 1 , wherein forming the liner layer comprises forming a layer of tungsten sulfide, tungsten selenide, molybdenum sulfide, molybdenum selenide, or combinations thereof.

11. A method, comprising:

forming a source/drain (S/D) region on a substrate;

forming a gate structure on the substrate;

depositing a dielectric layer on the S/D region;

forming a contact opening in the dielectric layer to expose a top surface of the S/D region;

forming a liner layer in the contact opening and on sidewalls of the dielectric layer;

depositing, after removing a portion of the liner layer from the top surface of the S/D region, a chalcogen material layer on the top surface of the S/D region;

depositing a metal layer on the chalcogen material layer; and

forming a contact plug in the contact opening and on the liner layer.

12. The method of claim 11 , wherein forming the liner layer comprises forming a layer of transition metal chalcogenide material.

13. The method of claim 11 , wherein depositing the metal layer comprises depositing a layer of transition metal at a temperature between about 300° C. and about 800° C. with a plasma process.

14. The method of claim 11 , wherein forming the liner layer comprises:

depositing a transition metal layer on the top surface of the S/D region and on the sidewalls of the dielectric layer in the contact opening prior to depositing the chalcogen material layer; and

exposing the transition metal layer to a chalcogen-based gas to form a transition metal chalcogenide layer on the top surface of the S/D region and on the sidewalls of the dielectric layer in the contact opening.

15. The method of claim 14 , further comprising etching a portion of the transition metal chalcogenide layer on the top surface of the S/D region.

16. A method, comprising:

forming first and second fin structures on a substrate;

forming a gate structure on the substrate;

forming a source/drain (S/D) region on the first and second fin structures;

depositing a dielectric layer on the S/D region;

forming an opening in the dielectric layer;

forming a first transition metal chalcogenide (TMC) layer on a sidewall of the dielectric layer in the opening and on a top surface of the S/D region in the opening;

removing a portion of the first TMC layer from the top surface of the S/D region;

forming a second TMC layer on the top surface of the S/D region and in contact with the first TMC layer; and

forming a contact plug on the first and second TMC layers.

17. The method of claim 16 , wherein forming the first TMC layer comprises depositing a transition metal layer on the sidewall of the dielectric layer.

18. The method of claim 16 , wherein forming the first TMC layer comprises forming a layer of sulfide, selenide, or telluride on the sidewall of the dielectric layer.

19. The method of claim 16 , wherein forming the second TMC layer comprises:

depositing a chalcogen material layer on the top surface of the S/D region; and

depositing a transition metal layer on the chalcogen material layer.

20. The method of claim 11 , further comprising performing a plasma treatment with a hydrogen gas on the metal layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 60089 FRAME: 794. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 8, 2025
From: KHADERBAD, MRUNAL ABHIJITH; WOON, WEI-YEN; LIN, CHENG-MING; LIN, HAN-YU; CHEN, SZU-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 070765/0770 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: KHADERBAD, MRUNAL ABHIJITH; WOON, WEI-YEN; LIN, CHENG-MING; LIN, HAN-YU; CHEN, SZU-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060089/0794 →
Continuity (2)
Provisional Application 63166573 · Mar 26, 2021
Related Publication 20220310800A1 · Sep 29, 2022
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