IP Library Granted Patent US 12,205,919
Granted Patent B2
US 12,205,919 · App. 17/555,709 · Granted Jan 21, 2025

Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module

Inventors: Chuan Cheah (Torrance, CA); Josef Hoeglauer (Heimstetten, DE); Tobias Polster (Villach, AT)
Assignee: Infineon Technologies AG
H01L24/24H01L21/568H01L21/78H01L23/5389H01L24/82H01L25/072H01L25/50H01L29/401H01L23/3736H01L29/45H01L2224/24137H01L2224/24155H01L2224/82106
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,205,919
App. No.
17/555,709
Granted
Jan 21, 2025
Kind
B2
Abstract

A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

Claims (11)

1. A method of processing a semiconductor wafer, the method comprising:

forming an electronic device at each die location of the semiconductor wafer;

partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location;

partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and

after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies,

wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition.

2. The method of claim 1 , wherein the partially formed frontside metallization and the partially formed backside metallization both comprise Al (aluminum).

3. The method of claim 1 , wherein the partially formed frontside metallization and the partially formed backside metallization both comprise AlCu (aluminum copper).

4. The method of claim 1 , wherein the partially formed frontside metallization is a multi-layer stack of different metals and/or metal alloys, and wherein the partially formed backside metallization comprises the same multi-layer stack of different metals and/or metal alloys as the partially formed frontside metallization.

5. The method of claim 1 , wherein the electronic device included in each individual semiconductor die is a vertical power transistor, wherein a gate electrode and a source electrode of the vertical power transistor is disposed at a first side of each individual semiconductor die, wherein a drain electrode of the vertical power transistor die is disposed at a second side of each individual semiconductor die opposite the first side, wherein the partially formed frontside metallization of each individual semiconductor die is patterned and forms the gate electrode and the source electrode of the vertical power transistor, and wherein the partially formed backside metallization of each individual semiconductor die forms the drain electrode of the vertical power transistor.

6. The method of claim 1 , wherein the electronic device included in each individual semiconductor die is a driver or controller for a power transistor, wherein each electrode of the driver or controller is disposed at a first side of each individual semiconductor die, wherein the partially formed frontside metallization of each individual semiconductor die is patterned and forms each electrode of the driver or controller, and wherein the partially formed backside metallization of each individual semiconductor die forms a heat dissipation structure at a second side opposite the first side.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 063028/0593 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2021
From: HOEGLAUER, JOSEF; POLSTER, TOBIAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 058429/0400 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2021
From: CHEAH, CHUAN
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 058429/0457 →
Continuity (1)
Related Publication 20230197663A1 · Jun 22, 2023
References Cited (6)
US 6023100A · Tao et al. · 2000 [cited by applicant]
US 20020163083A1 · Hatano et al. · 2002 [cited by applicant]
US 20040224495A1 · Young · 2004 [cited by applicant]
US 20050221554A1 · Huang · 2005 [cited by applicant]
US 20080191359A1 · Koller · 2008 [cited by examiner]
US 20110240354A1 · Furuhata · 2011 [cited by examiner]