SRAM with nanoribbon width modulation for greater read stability
Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.
1 . A static random-access memory (SRAM) cell structure, comprising:
a first transistor comprising a first portion of a stack of nanoribbons that have first ribbon widths; and
a second transistor of a same conductivity type as the first transistor, the second transistor comprising a second portion of the stack of nanoribbons, contiguous with the first portion, wherein the second portion has second ribbon widths, larger than the first ribbon widths, and wherein a centerline of the first portion of the stack of nanoribbons is colinear with a centerline of the second portion of the stack of nanoribbons.
2 . The SRAM cell structure of claim 1 , wherein the first transistor has n-type conductivity, and a transition between the first ribbon widths and the second ribbon widths is encapsulated by an n-type impurity-doped semiconductor material.
3 . The SRAM cell structure of claim 2 , wherein a first portion of the n-type impurity-doped semiconductor material adjacent to the first portion of the stack of nanoribbons has a narrower total width than a second portion of the n-type impurity-doped semiconductor material adjacent to the second portion of the stack of nanoribbons.
4 . The SRAM cell structure of claim 2 , further comprising a metallization feature in contact with the n-type impurity-doped semiconductor material, wherein the transition between the first ribbon widths and the second ribbon widths is under the metallization feature.
5 . The SRAM cell structure of claim 1 , wherein a transition between the first ribbon widths and the second ribbon widths is between a gate electrode of the first transistor and an n-type impurity-doped semiconductor material of the second transistor.
6 . The SRAM cell structure of claim 1 , wherein a transition between the first ribbon widths and the second ribbon widths is between a gate electrode of the second transistor and an n-type impurity-doped semiconductor material of the first transistor.
7 . The SRAM cell structure of claim 1 , wherein the first transistor is a pass-gate transistor and the second transistor is a pull-down transistor, and the SRAM cell structure further comprises
a second pass-gate transistor comprising a first portion of a second stack of nanoribbons having the first ribbon widths; and
a second pull-down transistor comprising a second portion of the second stack of nanoribbons having the second ribbon widths, wherein a centerline of the first portion of the second stack of nanoribbons is colinear with a centerline of the second portion of the second stack of nanoribbons.
8 . The SRAM cell structure of claim 1 , wherein the first transistor is a pass-gate transistor and the second transistor is a pull-down transistor, and the SRAM cell structure further comprises a pair of pull-up transistors comprising a stack of nanoribbons having at most the first ribbon widths.
9 . The SRAM cell structure of claim 8 , wherein the pull-up transistors comprise a stack of nanoribbons having third ribbon widths less than the second ribbon widths.
10 . A static random-access memory (SRAM) cell structure, comprising:
a first transistor comprising a first portion of a stack of nanoribbons that have first ribbon widths; and
a second transistor of a same conductivity type as the first transistor, the second transistor comprising a second portion of the stack of nanoribbons, wherein the second portion has second ribbon widths, larger than the first ribbon widths, and wherein a transition between the first ribbon widths and the second ribbon widths is encapsulated in an n-type impurity-doped source or drain material.
11 . The SRAM cell structure of claim 10 , wherein a centerline of the first portion of nanoribbons is colinear with a centerline of the second portion of nanoribbons.
12 . The SRAM cell structure of claim 10 , wherein a centerline of the first portion of the stack of nanoribbons is laterally offset from the second portion of the stack of nanoribbons by an amount substantially equal to a difference between the first and second ribbon widths.
13 . The SRAM cell structure of claim 12 , wherein a first side of the first portion of the stack of nanoribbons colinear with a first side of the second portion of the stack of nanoribbons faces an exterior of the cell structure.
14 . The SRAM cell structure of claim 12 , wherein a first side of the first portion of the stack of nanoribbons colinear with a first side of the second portion of the stack of nanoribbons is facing an interior of the cell structure.
15 . The SRAM cell structure of claim 12 , wherein a first portion of the n-type impurity-doped source or drain material adjacent to the first portion of the stack of nanoribbons has a narrower total width than a second portion of the n-type impurity-doped source or drain material adjacent to the second portion of the stack of nanoribbons.
16 . The SRAM cell structure of claim 12 , further comprising a metallization feature in contact with the n-type impurity-doped source or drain material, wherein the transition between the first ribbon widths and the second ribbon widths is under the metallization feature.
17 . The SRAM cell structure of claim 12 , wherein the first transistor is a pass-gate transistor and the second transistor is a pull-down transistor, and the SRAM cell structure further comprises a pair of pull-up transistors comprising a stack of nanoribbons having at most the first ribbon widths.
18 . The SRAM cell structure of claim 17 , wherein the pull-up transistors comprise a stack of nanoribbons having third ribbon widths less than the second ribbon widths.
19 . A device comprising:
a microprocessor comprising:
an arithmetic logic unit; and
a cache memory comprising an SRAM array, wherein the SRAM array comprises a plurality of bit-cells and each bit cell comprises:
the SRAM structure of claim 1 ; and
a power supply coupled to power the microprocessor.