Current mode multi-input maximum signal detector
A maximum current detection circuit with multiple input current ports and a maximum current port generates, on the maximum current port, a maximum current corresponding to the largest input current on one of the input current ports. The maximum current detection circuit includes multiple current mirror circuits, each controlled by one of the input currents. Each of the current mirror circuits includes outputs, each coupled to a respective one of the input current ports and the maximum current port. The current mirror circuit controlled by the largest input current becomes the dominant source for the input currents on each of the input current ports and also drives the maximum current on the maximum current port. The input currents may be single-ended or differential signals. The input currents may be respectively delayed signals of a windowing circuit in an envelope tracking circuit controlling a power amplifier of a wireless device.
1. A maximum current detection circuit comprising:
a first current port;
a second current port;
a maximum current port;
a first current mirror circuit comprising:
a first input coupled to the first current port;
a first mirror input coupled to the second current port; and
a first mirror output coupled to the maximum current port; and
a second current mirror circuit comprising:
a second input coupled to the second current port;
a second mirror input coupled to the first current port; and
a second mirror output coupled to the maximum current port.
2. The maximum current detection circuit of claim 1 , wherein:
the first current mirror circuit comprises:
a first transistor, a second transistor, and a third transistor, each comprising:
a source coupled to a supply voltage input; and
a gate coupled to the first current port;
wherein:
a drain of the first transistor is coupled to the first current port;
a drain of the second transistor is coupled to the second current port; and
a drain of the third transistor is coupled to the maximum current port; and
the second current mirror circuit comprises:
a fourth transistor, a fifth transistor, and a sixth transistor, each comprising:
a source coupled to the supply voltage input; and
a gate coupled to the second current port;
wherein:
a drain of the fourth transistor is coupled to the second current port;
a drain of the fifth transistor is coupled to the first current port; and
a drain of the sixth transistor is coupled to the maximum current port.
3. The maximum current detection circuit of claim 2 , further comprising:
a third current port; and
a third current mirror circuit comprising:
a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, each comprising:
a source coupled to the supply voltage input; and
a gate coupled to a third current port;
wherein:
a drain of the seventh transistor is coupled to the third current port;
a drain of the eighth transistor is coupled to the first current port;
a drain of the ninth transistor is coupled to the second current port;
a drain of the tenth transistor is coupled to the maximum current port;
the first current mirror circuit further comprises an eleventh transistor comprising:
a source coupled to the supply voltage input;
a gate coupled to the first current port; and
a drain coupled to the third current port; and
the second current mirror circuit further comprises a twelfth transistor comprising:
a source coupled to the supply voltage input;
a gate coupled to the second current port; and
a drain coupled to the third current port.
4. The maximum current detection circuit of claim 2 , wherein the second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor are a same size as the first transistor.
5. The maximum current detection circuit of claim 2 , wherein the second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor are configured to have a same current capacity as the first transistor.
6. The maximum current detection circuit of claim 2 , further comprising:
an envelope signal input;
a first delay circuit comprising a first signal input coupled to the envelope signal input and configured to generate a first delayed envelope signal on a signal delay output, the first delayed envelope signal comprising a current amplitude based on a voltage amplitude on the envelope signal input delayed by a first delay; and
a second delay circuit comprising a second signal input coupled to the envelope signal input and configured to generate a second delayed envelope signal on a signal delay output, the second delayed envelope signal comprising the current amplitude based on the voltage amplitude on the envelope signal input delayed by a second delay;
wherein:
the signal delay output of the first delay circuit is coupled to the first current port; and
the signal delay output of the second delay circuit is coupled to the second current port.
7. The maximum current detection circuit of claim 3 , further comprising:
an envelope signal input;
a first delay circuit comprising a signal delay input coupled to the envelope signal input and configured to generate a first delayed envelope signal on a first signal delay output, the first delayed envelope signal comprising a current amplitude based on a voltage amplitude on the envelope signal input delayed by a first delay;
a second delay circuit comprising a signal delay input coupled to the envelope signal input and configured to generate a second delayed envelope signal on a second signal delay output, the second delayed envelope signal comprising the current amplitude based on a voltage amplitude on the envelope signal input delayed by a second delay and
a third delay circuit comprising a signal delay input coupled to the envelope signal input and configured to generate a third delayed envelope signal on a third signal delay output, the third delayed envelope signal comprising a current amplitude based on a voltage amplitude on the envelope signal input delayed by a third delay;
wherein:
the first signal delay output is coupled to the first current port;
the second signal delay output is coupled to the second current port; and
the third signal delay output is coupled to the third current port.
8. The maximum current detection circuit of claim 2 , wherein:
the first current port comprises a first P-type current port;
the second current port comprises a second P-type current port;
the maximum current port comprises a maximum P-type current port;
the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor comprise a first P-type transistor, second P-type transistor, third P-type transistor, fourth P-type transistor, fifth P-type transistor, and sixth P-type transistor; and
the maximum current detection circuit further comprises:
a first N-type current port;
a second N-type current port;
a maximum N-type current port:
a first N-type current mirror circuit comprising:
a first N-type transistor, a second N-type transistor, and a third N-type transistor, each comprising:
a source coupled to a reference voltage input; and
a gate coupled to the first N-type current port;
wherein:
a drain of the first N-type transistor is coupled to the first N-type current port;
a drain of the second N-type transistor is coupled to the second N-type current port; and
a drain of the third N-type transistor is coupled to the maximum N-type current port; and
a second N-type current mirror circuit comprises:
a fourth N-type transistor, a fifth N-type transistor, and a sixth N-type transistor, each comprising:
a source port coupled to the reference voltage input; and
a gate port coupled to the second N-type current port;
wherein:
a drain port of the fourth N-type transistor is coupled to the second N-type current port;
a drain port of the fifth N-type transistor is coupled to the first N-type current port; and
a drain port of the sixth N-type transistor is coupled to the maximum N-type current port.
9. The maximum current detection circuit of claim 2 , further comprising:
a first resistor coupled between the drain of the first transistor and the first current port; and
a second resistor coupled between the drain of the second transistor and the second current port.
10. The maximum current detection circuit of claim 8 , further comprising:
a first resistor coupled between the drain of the first P-type transistor and the first P-type current port;
a second resistor coupled between the drain of the second P-type transistor and the second P-type current port;
a third resistor coupled between the drain of the first N-type transistor and the first N-type current port; and
a fourth resistor coupled between the drain of the second N-type transistor and the second N-type current port.
11. The maximum current detection circuit of claim 2 , further comprising:
an output transistor comprising:
a source coupled to the drain of the third transistor and the drain of the sixth transistor; and
a drain coupled to the maximum current port.
12. The maximum current detection circuit of claim 9 , further comprising:
an output transistor comprising:
a source coupled to the drain of the third transistor and the drain of the sixth transistor; and
a drain coupled to the maximum current port.
13. The maximum current detection circuit of claim 8 , further comprising:
a P-type output transistor comprising:
a source coupled to the drain of the third P-type transistor and the drain of the sixth P-type transistor; and
a drain coupled to the maximum current port; and
an N-type output transistor comprising:
a source coupled to the drain of the third N-type transistor and the drain of the sixth N-type transistor; and
a drain coupled to the maximum current port.
14. The maximum current detection circuit of claim 2 , further comprising:
a first cascode transistor comprising:
a source coupled to the drain of the first transistor; and
a drain coupled to the first current port; and
a second cascode transistor comprising:
a source coupled to the drain of the second transistor; and
a drain coupled to the second current port;
a third cascode transistor comprising:
a source coupled to the drain of the third transistor; and
a drain coupled to the maximum current port;
a fourth cascode transistor comprising:
a source coupled to the drain of the fourth transistor; and
a drain coupled to the second current port; and
a fifth cascode transistor comprising:
a source coupled to the drain of the fifth transistor; and
a drain coupled to the first current port; and
a sixth cascode transistor comprising:
a source coupled to the drain of the sixth transistor; and
a drain coupled to the maximum current port.
15. The maximum current detection circuit of claim 8 , further comprising:
a first N-type cascode transistor comprising:
a source coupled to the drain of the first N-type transistor; and
a drain coupled to the first N-type current port; and
a second N-type cascode transistor comprising:
a source coupled to the drain of the second N-type transistor; and
a drain coupled to the second N-type current port;
a third N-type cascode transistor comprising:
a source coupled to the drain of the third N-type transistor; and
a drain coupled to the maximum N-type current port;
a fourth N-type cascode transistor comprising:
a source coupled to the drain of the fourth N-type transistor; and
a drain coupled to the second N-type current port; and
a fifth N-type cascode transistor comprising:
a source coupled to the drain of the fifth N-type transistor; and
a drain coupled to the first N-type current port;
a sixth N-type cascode transistor comprising:
a source coupled to the drain of the sixth N-type transistor; and
a drain coupled to the maximum N-type current port;
a first P-type cascode transistor comprising:
a source coupled to the drain of the first P-type transistor; and
a drain coupled to the first P-type current port; and
a second P-type cascode transistor comprising:
a source coupled to the drain of the second P-type transistor; and
a drain coupled to the second P-type current port;
a third P-type cascode transistor comprising:
a source coupled to the drain of the third P-type transistor; and
a drain coupled to the maximum P-type current port;
a fourth P-type cascode transistor comprising:
a source coupled to the drain of the fourth P-type transistor; and
a drain coupled to the second P-type current port; and
a fifth P-type cascode transistor comprising:
a source coupled to the drain of the fifth P-type transistor; and
a drain coupled to the first P-type current port; and
a sixth P-type cascode transistor comprising:
a source coupled to the drain of the sixth P-type transistor; and
a drain coupled to the maximum P-type current port.
16. A wireless device comprising:
a transceiver configured to generate, based on a received analog signal:
an output analog signal on a signal output; and
an envelope signal based on a magnitude envelope of the output analog signal on an envelope output;
a delay circuit configured to:
receive the envelope signal on a signal input;
generate a first delayed envelope signal based on the envelope signal on a first delay output;
generate a second delayed envelope signal based on the envelope signal on a second delay output; and
generate a third delayed envelope signal based on the envelope signal on a third delay output;
a maximum current detection circuit comprising:
a first current port coupled to the first delay output;
a second current port coupled to the second delay output;
a third current port coupled to the third delay output;
a maximum current port;
a first current mirror circuit comprising:
a first input coupled to the first current port;
a first mirror input coupled to the second current port; and
a first mirror output coupled to the maximum current port; and
a second current mirror circuit comprising:
a second input coupled to the second current port;
a second mirror input coupled to the first current port; and
a second mirror output coupled to the maximum current port; and
a power amplifier configured to amplify the output analog signal based on a supply voltage based on a maximum current on the maximum current port.