Memory device
A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
1. A memory device comprising:
a first memory cell array including a first stacked body, the first stacked body including a plurality of first electrode layers each extending in a first direction; and
a peripheral circuit facing the first memory cell array and driving the first memory cell array, the peripheral circuit and the first memory cell array being arranged in a second direction, the second direction crossing the first direction, the plurality of first electrode layers being stacked in the second direction, wherein
the plurality of first electrode layers each has a length along the first direction such that a first-first electrode layer of the plurality of first electric layers has a length shorter than a length of a second-first electrode layer of the plurality of first electric layers, and
the first-first electrode layer is positioned between the peripheral circuit and the second-first electrode layer.
2. The device according to claim 1 , further comprising:
a first contact line connected to each of the plurality of first electrode layers; and
a second contact line connected to the peripheral circuit, the second contact line being electrically connected to the first contact line.
3. The device according to claim 2 , further comprising:
a first bonding electrode connected to the first contact line; and
a second bonding electrode connected to the second contact line, wherein
the second bonding electrode is connected to the first bonding electrode at a first bonding surface,
the first bonding electrode has a first diameter in a vicinity of the first bonding surface,
the second bonding electrode has a second diameter in a vicinity of the first bonding surface,
the first diameter is greater than a diameter of the first contact line, and
the second diameter is greater than a diameter of the second contact line.
4. The device according to claim 2 , further comprising:
a second memory cell array provided on the first memory cell array, the first memory cell array being provided between the peripheral circuit and the second memory cell array, the second memory cell array including a second stacked body, the second stacked body including a plurality of second electrode layers each extending in the first direction, the plurality of second electrode layers being stacked in the second direction, wherein
the plurality of second electrode layers each has a length along the first direction such that a first-second electrode layer of the plurality of second electric layers has a length shorter than a length of a second-second electrode layer of the plurality of second electric layers, and
the first-second electrode layer is positioned between the first memory cell array and the second-second electrode layer.
5. The device according to claim 4 , further comprising:
a third contact line connected to each of the plurality of second electrode layers, the third contact line being electrically connected to the first contact line.
6. The device according to claim 5 , further comprising:
a third bonding electrode connected to the first contact line, the first contact line having first and second end arranged along the second direction, the first end being electrically connected to the peripheral circuit, the second end being connected to the third bonding electrode; and
a fourth bonding electrode connected to the third contact line, wherein
the third bonding electrode is connected to the fourth bonding electrode at a second bonding surface,
the third bonding electrode has a third diameter in a vicinity of the second bonding surface,
the fourth bonding electrode has a fourth diameter in a vicinity of the second bonding surface,
the third diameter is greater than a diameter of the first contact line, and
the fourth diameter is greater than a diameter of the third contact line.
7. The device according to claim 1 , further comprising:
a fourth contact line connected to the peripheral circuit, wherein
the peripheral circuit is configured to receive date via the fourth contact line.
8. The device according to claim 7 , wherein
the peripheral circuit includes a first region and a second region, the first region of the peripheral circuit facing the first memory cell array, the second region of the peripheral circuit being provided without facing the first memory cell array, and
the fourth contact line is connected to the second region of the peripheral circuit.