IP Library Granted Patent US 12,237,367
Granted Patent B2
US 12,237,367 · App. 17/593,034 · Granted Feb 25, 2025

Semiconductor structures and methods for forming the same

Inventors: Junchao Zhang (Hefei, CN); Cheng Yeh Hsu (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H01L29/0649H01L21/76224H01L21/823481
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Quick Facts
Patent No.
US 12,237,367
App. No.
17/593,034
Granted
Feb 25, 2025
Kind
B2
Abstract

A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H 2.

Claims (22)

1. A method for forming a semiconductor structure, comprising:

providing a semiconductor substrate, a surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction;

etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses;

covering surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer;

removing the metal layer covering the surfaces of the first recesses and the second recesses by a chemical mechanical polishing process to form recesses from which the adhesive layer is exposed;

pre-etching selectively the adhesive layer exposed from second recesses in the shallow trench isolation areas in the direction perpendicular to the first direction, a depth of the pre-etching the adhesive layer being defined as H 0 ; and

secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form contact holes, depths of the adhesive layer in the contact holes being defined as H 2 , the H 0 being less than the H 2 ;

wherein an upper surface of the adhesive layer in the contact holes is deeper than an upper surface of the adhesive layer in the first recesses.

2. The method for forming a semiconductor structure according to claim 1 , prior to the etching the active areas and the shallow trench isolation areas to form the first recesses and the second recesses, the method further comprising:

depositing a sacrificial layer on the surface of the semiconductor substrate.

3. The method for forming a semiconductor structure according to claim 2 , wherein

the sacrificial layer is made of at least one of silicon dioxide, silicon nitride, silicon oxynitride, polycrystalline silicon, monocrystalline silicon, or carbon.

4. The method for forming a semiconductor structure according to claim 1 , wherein

a range of the H 0 is from 10 nanometers to 20 nanometers.

5. The method for forming a semiconductor structure according to claim 1 , the secondarily etching the metal layer and the adhesive layer further comprising:

continuously etching the adhesive layer and the metal layer to form contact holes in the-direction perpendicular to the first direction, a depth of the secondarily etching the adhesive layer and the metal layer being defined as H 1 , the H 1 being less than the H 2 .

6. The method for forming a semiconductor structure according to claim 5 , wherein

a range of the H 1 is from 60 nanometers to 70 nanometers.

7. The method for forming a semiconductor structure according to claim 1 , wherein

a range of the H 2 is from 71 nanometers to 80 nanometers.

8. The method for forming a semiconductor structure according to claim 1 , wherein

the adhesive layer is made of titanium nitride, and the metal layer is made of tungsten.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2021
From: ZHANG, JUNCHAO; HSU, CHENG YEH
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 057388/0175 →
Priority Claims (1)
CN 202010279732.4 · Apr 10, 2020 · national
Continuity (1)
Related Publication 20220310782A1 · Sep 29, 2022
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