Backside routing implementation in SRAM arrays
Various implementations of backside and topside routing of bitlines and wordlines in memory arrays are disclosed. Bitlines in backside and topside metal layers may be alternated between adjacent bit cells in a memory array. Alternating the location of the bitlines between bit cells in the memory array may reduce bitline capacitance in a memory array. Placing wordlines in backside metal layers may allow dual wordlines to be implemented across a span of bit cells in a memory array. The dual wordlines may be alternately connected to adjacent bit cells, thereby allowing selective toggling of bit cells based on the wordline transmitting a control signal.
1 . A memory apparatus, comprising:
a plurality of bit cells, the bit cells being adjacently positioned, wherein the plurality of bit cells includes a first bit cell adjacent a second bit cell;
a plurality of topside metal layers located above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells;
a plurality of backside metal layers located below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells;
a first bitline spanning the first bit cell in a first direction, wherein the first bitline includes a first wire located in a first metal layer of the topside metal layers, and wherein the first wire connects to the first bit cell;
a second bitline spanning the second bit cell in the first direction, wherein the second bitline includes a second wire located in a first metal layer of the backside metal layers, and wherein the second wire connects to the second bit cell;
a first wordline spanning the first and second bit cells in a second direction, the second direction being orthogonal to the first direction, wherein the first wordline includes a third wire located in a second metal layer of the topside metal layers, the third wire connecting to the second bit cell to provide a first control signal to the second bit cell but not the adjacent first bit cell; and
a second wordline spanning the first and second bit cells in the second direction, wherein the second wordline includes a fourth wire located in a second metal layer of the backside metal layers, the fourth wire connecting to the first bit cell to provide a second control signal to the first bit cell but not the adjacent second bit cell.
2 . The apparatus of claim 1 , further comprising a third bitline spanning the first bit cell in the first direction, wherein the third bitline includes a fifth wire located in the first metal layer of the topside metal layers, and wherein the fifth wire connects to the first bit cell, and wherein the first wire and the fifth wire are configured as a complementary pair.
3 . The apparatus of claim 1 , further comprising a fourth bitline spanning the second bit cell in the first direction, wherein the fourth bitline includes a sixth wire located in the first metal layer of the backside metal layers, and wherein the sixth wire connects to the second bit cell, and wherein the second wire and the sixth wire are configured as a complementary pair.
4 . The apparatus of claim 1 , further comprising:
a third bit cell adjacent the second bit cell in the plurality of bit cells, the third bit cell being on an opposite side of the second bit cell from the first bit cell; and
a third bitline spanning the third bit cell, wherein the third bitline includes an additional wire located in the first metal layer of the topside metal layers, and wherein the additional wire connects to the third bit cell.
5 . The apparatus of claim 4 , further comprising:
a fourth bit cell adjacent the third bit cell in the plurality of bit cells, the fourth bit cell being on an opposite side of the third bit cell from the second bit cell; and
a fourth bitline spanning the fourth bit cell, wherein the fourth bitline includes an additional wire located in the first metal layer of the backside metal layers, and wherein the additional wire located in the second metal layer connects to the fourth bit cell.
6 . The apparatus of claim 1 , wherein the first bitline is parallel to the second bitline.
7 . The apparatus of claim 1 , wherein the bit cells are adjacently positioned in the second direction, and wherein the first bitline and the second bitline span the plurality of bit cells in the first direction.
8 . The apparatus of claim 1 , wherein the first wordline and the second wordline span the plurality of bit cells in the second direction.
9 . A memory apparatus, comprising:
a plurality of bit cells, the bit cells being adjacently positioned, wherein the plurality of bit cells includes a first bit cell adjacent a second bit cell;
a first metal layer located above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells;
a second metal layer located below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells;
a first wordline spanning the plurality of bit cells, wherein the first wordline includes a wire located in the first metal layer, and wherein the wire located in the first metal layer connects to and provides a first control signal to the first bit cell but not the adjacent second bit cell; and
a second wordline spanning the plurality of bit cells, wherein the second wordline includes a wire located in the second metal layer, and wherein the wire located in the second metal layer connects to and provides a second control signal to the second bit cell but not the adjacent first bit cell.
10 . The apparatus of claim 9 , further comprising a third bit cell adjacent the second bit cell in the plurality of bit cells, the third bit cell being on an opposite side of the second bit cell from the first bit cell, wherein the wire located in the first metal layer connects to the third bit cell.
11 . The apparatus of claim 10 , further comprising a fourth bit cell adjacent the third bit cell in the plurality of bit cells, the fourth bit cell being on an opposite side of the third bit cell from the second bit cell, wherein the wire located in the second metal layer connects to the fourth bit cell.
12 . The apparatus of claim 9 , wherein the bit cells are adjacently positioned in a first direction, and wherein the wire in the first wordline and the wire in the second wordline span the plurality of bit cells in the first direction.
13 . The apparatus of claim 9 , wherein the first wordline and the second wordline span the plurality of bit cells in a first direction, the apparatus further comprising:
a first bitline spanning the first bit cell in a second direction, the second direction being perpendicular to the first direction, wherein the first bitline includes an additional wire located in the first metal layer; and
a second bitline spanning the second bit cell in the second direction, wherein the second bitline includes an additional second wire located in the second metal layer.
14 . The apparatus of claim 9 , further comprising a wordline logic cell coupled to the first wordline and the second wordline, wherein the wordline logic cell is configured to provide separate control signals to the first wordline and the second wordline.
15 . The apparatus of claim 9 , wherein the first control signal and the second control signal are separate control signals.
16 . A memory apparatus, comprising:
a plurality of bit cells, the bit cells being adjacently positioned, wherein the plurality of bit cells includes a first bit cell adjacent a second bit cell;
a first metal layer located above the plurality of bit cells in a vertical dimension perpendicular to the plurality of bit cells;
a second metal layer located below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells;
a first pair of complementary bitlines spanning the first bit cell in a first direction, wherein the first pair of complementary bitlines includes two wires located in the first metal layer, and wherein the two wires located in the first metal layer connect to the first bit cell;
a second pair of complementary bitlines spanning the second bit cell in the first direction, wherein the second pair of complementary bitlines includes two wires located in the second metal layer, and wherein the two wires located in the second metal layer connect to the second bit cell;
a third metal layer located above the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells, the third metal layer being separated from the first metal layer;
a fourth metal layer located below the plurality of bit cells in the vertical dimension perpendicular to the plurality of bit cells, the fourth metal layer being separated from the second metal layer;
a first wordline spanning the first and second bit cells in a second direction, the second direction being perpendicular to the first direction, wherein the first wordline includes a first wordline wire located in the third metal layer, the first wordline wire being connected to the second bit cell to provide a first control signal to the second bit cell but not the adjacent first bit cell; and
a second wordline spanning the first and second bit cells in the second direction, wherein the second wordline includes a second wordline wire located in the fourth metal layer, the second wordline wire being connected to the first bit cell to provide a second control signal to the first bit cell but not the adjacent second bit cell.
17 . The apparatus of claim 16 , wherein the two wires located in the first metal layer connect to the first bit cell at spatially separated locations.
18 . The apparatus of claim 16 , wherein the two wires located in the second metal layer connect to the second bit cell at spatially separated locations.
19 . The apparatus of claim 16 , wherein the two wires located in the first metal layer are parallel, and wherein the two wires located in the second metal layer are parallel.
20 . The apparatus of claim 16 , wherein the first pair of complementary bitlines are parallel to the second pair of complementary bitlines.