3D vertical FET with top and bottom gate contacts
View Patent ↗A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
1. A method for forming a semiconductor device, comprising:
forming a vertical transistor on a substrate;
forming a gate structure disposed about a channel region of the vertical transistor, the vertical transistor having a top side and a bottom side;
forming bottom side metallization structures having at least one connection to the vertical transistor on a bottom side, the bottom side metallization structures including a power rail and a ground rail;
after forming the bottom side metallization structures, removing the substrate and flipping the vertical transistor; and
forming top side metallization structures, the top side metallization structures having at least one connection to the vertical transistor on the top side.
2. The method as recited in claim 1 , wherein the gate structure is contacted on the top side and the bottom side by gate contacts.
3. The method as recited in claim 1 , wherein the gate contacts are formed on opposite sides of a same gate structure on the top side and the bottom side.
4. The method as recited in claim 1 , wherein the vertical transistor is contacted on the top side and the bottom side.
5. The method as recited in claim 1 , wherein the top side includes far end of the line structures and the bottom side includes back end of the line (BEOL) structures.
6. The method as recited in claim 1 , wherein forming the top side metallization structures includes forming the top side metallization structures having at least one connection to the vertical transistor on the top side.
7. The method as recited in claim 1 , further comprising forming gate contacts to the gate structure on the top side and the bottom side.
8. The method as recited in claim 1 , wherein the vertical transistor is a part of a logic device and the logic device connects to the metallization structures on the top side and the bottom side.
9. The method as recited in claim 8 , wherein the logic device includes a logic device from a five track cell library.
10. The method as recited in claim 1 , further comprising forming gate contacts to the gate structure on the top side and the bottom side.
11. A method for forming a semiconductor device, comprising:
forming a vertical transistor on a substrate;
forming a gate structure disposed about a channel region of the vertical transistor, the vertical transistor having a top side and a bottom side;
forming bottom side metallization structures having at least one connection to the vertical transistor on the bottom side;
after forming the bottom side metallization structures, removing the substrate and flipping the vertical transistor; and
forming top side metallization structures.
12. The method as recited in claim 11 , wherein the gate structure is contacted on the top side and the bottom side by gate contacts.
13. The method as recited in claim 11 , wherein the gate contacts are formed on opposite sides of a same gate structure on the top side and the bottom side.
14. The method as recited in claim 11 , wherein the vertical transistor is contacted on the top side and the bottom side.
15. The method as recited in claim 11 , wherein the top side includes far end of the line structures and the bottom side includes back end of the line (BEOL) structures.
16. The method as recited in claim 11 , wherein forming the top side metallization structures includes forming the top side metallization structures having at least one connection to the vertical transistor on the top side.
17. The method as recited in claim 11 , further comprising forming gate contacts to the gate structure on the top side and the bottom side.
18. The method as recited in claim 17 , wherein the gate contacts are formed on opposite sides of a same gate structure on the top side and the bottom side.
19. The method as recited in claim 11 , wherein the vertical transistor is a part of a logic device and the logic device connects to the metallization structures on the top side and the bottom side.
20. The method as recited in claim 19 , wherein the logic device includes a logic device from a five track cell library.