Integrated circuit with buried power rail and methods of manufacturing the same
A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.
1. An integrated circuit comprising:
a first semiconductor substrate, the first semiconductor substrate being a bare semiconductor wafer;
a first dielectric layer on the first semiconductor substrate;
buried power rails accommodated in the first dielectric layer;
a second dielectric layer on the first dielectric layer and the buried power rails;
a third dielectric layer on the second dielectric layer;
a donor wafer on the third dielectric layer; and
a plurality of active devices, vias, and metal interconnects on or in the donor wafer.
2. The integrated circuit of claim 1 , wherein at least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer is a thermal oxide layer having a thickness in a range from approximately 0.1 μm to approximately 10 μm.
3. The integrated circuit of claim 1 , wherein:
the first dielectric layer is a thermal oxide layer having a thickness in a range from approximately 0.05 μm to approximately 9.8 μm,
the second dielectric layer is a thermal oxide layer having a thickness in a range from approximately 0.05 μm to approximately 0.1 μm, and
the third dielectric layer is a thermal oxide layer having a thickness in a range from approximately 0.05 μm to approximately 0.1 μm.
4. The integrated circuit of claim 1 , wherein the active devices are in the third dielectric layer and the metal interconnects are in the donor wafer.
5. The integrated circuit of claim 1 , wherein the donor wafer comprises a material selected from the group consisting of silicon (Si), silicon-germanium (SiGe), Ge, a Group III-V material, and combinations thereof.
6. The integrated circuit of claim 1 , wherein the donor wafer has a thickness in a range from approximately 30 nm to approximately 10 μm.
7. The integrated circuit of claim 1 , wherein the buried power rails have a thermal stability of at least approximately 700° C.
8. The integrated circuit of claim 1 , wherein the buried power rails comprise a refractive metal.
9. The integrated circuit of claim 8 , wherein the refractive metal is tungsten or ruthenium.
10. The integrated circuit of claim 1 , further comprising a liner between the buried power rails and the first dielectric layer.
11. The integrated circuit of claim 10 , wherein the liner comprises titanium nitride (TiN).
12. The integrated circuit of claim 1 , wherein the first dielectric layer is directly on the first semiconductor substrate.
13. The integrated circuit of claim 12 , wherein the buried power rails are accommodated in trenches in an upper surface of the first dielectric layer.
14. The integrated circuit of claim 1 , wherein the first dielectric layer is separated from the first semiconductor substrate by another dielectric layer.
15. The integrated circuit of claim 14 , further comprising a liner separating the buried power rails from the first dielectric layer and the another dielectric layer.
16. The integrated circuit of claim 15 , further comprising a fourth dielectric layer on the third dielectric layer, wherein the donor wafer is on the fourth dielectric layer, and wherein the active devices are in the fourth dielectric layer.