IP Library › Granted Patent US 12,412,854
Granted Patent B2
US 12,412,854 · App. 17/662,493 · Granted Sep 9, 2025

Semiconductor devices containing copper bonding pads with different conductive barrier layers and methods for forming the same

Inventors: Linghan Chen (Yokkaichi, JP); Lin Hou (Leuven, BE)
Assignee: Sandisk Technologies, Inc.
H01L24/08H01L24/03H01L24/05H01L24/80H01L25/0657H01L25/18H01L25/50H01L2224/03616H01L2224/05082H01L2224/05147H01L2224/05157H01L2224/05166H01L2224/05176H01L2224/05181H01L2224/0807H01L2224/08145H01L2224/80895H01L2224/80896H01L2924/04941H01L2924/04953H01L2924/1431H01L2924/14511
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Quick Facts
Patent No.
US 12,412,854
App. No.
17/662,493
Granted
Sep 9, 2025
Kind
B2
Abstract

Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

Claims (34)

1. A bonded assembly, comprising:

a first semiconductor die comprising first semiconductor devices and a first bonding pad, wherein the first bonding pad comprises a first copper material portion and a first conductive barrier layer comprising a first conductive barrier material having a higher electrochemical potential than copper located between the first semiconductor devices and the first copper material portion; and

a second semiconductor die comprising second semiconductor devices and a second bonding pad, wherein the second bonding pad comprises a second copper material portion and a second conductive barrier layer comprising a second conductive barrier material having a lower electrochemical potential than copper located between the second semiconductor devices and the second copper material portion;

wherein:

the second bonding pad is bonded to the first bonding pad;

a bonding interface between the first bonding pads and the second bonding pads comprises a non-planar interface at which a convex surface of the first copper material portion contacts a concave surface of the second copper material portion;

the first semiconductor die further comprises:

at least one first dielectric material layer;

first metal interconnect structures embedded in the at least one first dielectric material layer and electrically connected to the first semiconductor devices; and

a first bonding-level dielectric layer, wherein the first bonding pad is embedded in the first bonding-level dielectric layer and electrically connected to at least one of the first metal interconnect structures; and

the second semiconductor die further comprises:

at least one second dielectric material layer;

second metal interconnect structures embedded in the at least one second dielectric material layer and electrically connected to the second semiconductor devices; and

a second bonding-level dielectric layer, wherein the second bonding pad is embedded in the second bonding-level dielectric layer and electrically connected to at least one of the second metal interconnect structures;

an entirety of a periphery of the convex surface of the first copper material portion is adjoined to a surface of the first bonding-level dielectric layer; and

the first conductive barrier layer is vertically spaced from the second bonding pad by a peripheral portion of the first copper material portion that contacts a sidewall of the first bonding-level dielectric layer.

2. A bonded assembly, comprising:

a first semiconductor die comprising first semiconductor devices and a first bonding pad, wherein the first bonding pad comprises a first copper material portion and a first conductive barrier layer comprising a first conductive barrier material having a higher electrochemical potential than copper located between the first semiconductor devices and the first copper material portion; and

a second semiconductor die comprising second semiconductor devices and a second bonding pad, wherein the second bonding pad comprises a second copper material portion and a second conductive barrier layer comprising a second conductive barrier material having a lower electrochemical potential than copper located between the second semiconductor devices and the second copper material portion;

wherein:

the second bonding pad is bonded to the first bonding pad;

wherein a bonding interface between the first bonding pads and the second bonding pads comprises a non-planar interface at which a convex surface of the first copper material portion contacts a concave surface of the second copper material portion;

the first semiconductor die further comprises:

at least one first dielectric material layer;

first metal interconnect structures embedded in the at least one first dielectric material layer and electrically connected to the first semiconductor devices; and

a first bonding-level dielectric layer, wherein the first bonding pad is embedded in the first bonding-level dielectric layer and electrically connected to at least one of the first metal interconnect structures; and

the second semiconductor die further comprises:

at least one second dielectric material layer;

second metal interconnect structures embedded in the at least one second dielectric material layer and electrically connected to the second semiconductor devices; and

a second bonding-level dielectric layer, wherein the second bonding pad is embedded in the second bonding-level dielectric layer and electrically connected to at least one of the second metal interconnect structures;

the second bonding-level dielectric layer is in direct contact with the first bonding-level dielectric layer at a horizontal plane;

a horizontal surface of a vertically-extending portion of the second conductive barrier layer is located within the horizontal plane; and

an annular surface of a vertically-extending portion of the first conductive barrier layer that faces the second semiconductor die and is most proximal to the second semiconductor die is vertically spaced from the horizontal plane by a peripheral portion of the first copper material portion.

3. The bonded assembly of claim 2 , wherein the annular surface comprises a non-planar grooved surface having a concave vertical cross-sectional profile, and the non-planar grooved surface is contacted entirely by the first copper material portion.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2022
From: CHEN, LINGHAN; HOU, LIN
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 059871/0370 →
Continuity (1)
Related Publication 20230361066A1 · Nov 9, 2023
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