Semiconductor packages with thermal lid and methods of forming the same
Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.
1 . A semiconductor device comprising:
a semiconductor chip package bonded to a substrate and surrounded by an encapsulant;
a thermal interface material on the semiconductor chip package; and
a lid over the semiconductor chip package, the encapsulant, and the substrate, the lid comprising a wedge feature interfacing the thermal interface material, wherein the wedge feature comprises a tapered edge, the tapered edge interfacing the thermal interface material.
2 . The semiconductor device of claim 1 , wherein the wedge feature comprises a first base edge and a second base edge, the first base edge and the second base edge interfacing the thermal interface material.
3 . The semiconductor device of claim 2 , wherein the wedge feature comprises a backend edge intersecting the first base edge and the second base edge, the backend edge interfacing the thermal interface material.
4 . The semiconductor device of claim 1 , wherein the wedge feature comprises a ring configuration, the tapered edge extending along an inner perimeter of the ring configuration.
5 . The semiconductor device of claim 4 , wherein the wedge feature comprises a backend base edge extending along an outer perimeter of the ring configuration, the backend base edge interfacing the thermal interface material.
6 . The semiconductor device of claim 4 , wherein the wedge feature comprises a backend base edge extending along an outer perimeter of the ring configuration, the backend base edge being located outside of a perimeter of the thermal interface material.
7 . A semiconductor device comprising:
a device die bonded to a substrate, the device die being surrounded by an encapsulant;
a thermal interface material disposed on a surface of the device die opposite the substrate, the thermal interface material in physical contact with both the device die and the encapsulant; and
a thermal lid comprising an angled projection, the thermal interface material extending between the thermal lid and the device die, the thermal interface material also extending between the angled projection and the encapsulant.
8 . The semiconductor device of claim 7 , wherein the thermal interface material has a first thickness between the device die and the thermal lid and a second thickness between the encapsulant and the angled projection, the second thickness being less than the first thickness.
9 . The semiconductor device of claim 7 , wherein a thickness of the thermal interface material is graded from a maximum thickness at a tapered edge of the angled projection to a minimum thickness at an edge of the encapsulant.
10 . The semiconductor device of claim 7 , wherein the angled projection comprises a backend edge aligned to a corner of the encapsulant.
11 . The semiconductor device of claim 7 , wherein the angled projection comprises a backend edge that extends beyond an outer edge of the encapsulant.
12 . The semiconductor device of claim 8 , wherein the angled projection has a ring configuration and a backend edge of the ring configuration is aligned to an edge of the encapsulant.
13 . The semiconductor device of claim 8 , wherein the angled projection has a ring configuration and a backend edge of the ring configuration extends past the encapsulant.
14 . A semiconductor device comprising:
a three-dimensional integrated circuit package bonded to a substrate, the three-dimensional integrated circuit package comprising a semiconductor die embedded within an encapsulant;
a thermal interface material on the three-dimensional integrated circuit package; and
a heat spreader over the thermal interface material, the thermal interface material conforming to a beveled surface of the heat spreader, wherein the thermal interface material has a first thickness over the semiconductor die and a second thickness over the encapsulant, the second thickness being less than the first thickness.
15 . The semiconductor device of claim 14 , wherein the thickness of the thermal interface material is graded from a greatest thickness at a tapered edge of the beveled surface to a minimum thickness at an edge of the encapsulant.
16 . The semiconductor device of claim 15 , wherein the beveled surface has an angle of between about 5° and about 45°.
17 . The semiconductor device of claim 14 , wherein the beveled surface of the heat spreader has a first lateral extent being aligned to a second lateral extent of the encapsulant.
18 . The semiconductor device of claim 14 , wherein the beveled surface of the heat spreader has a first lateral extent that extends outside of a second lateral extent of the encapsulant.
19 . The semiconductor device of claim 1 , wherein the thermal interface material has a thermal conductivity between about 3 W/m·K to about 5 W/m·K.
20 . The semiconductor device of claim 14 , wherein the thermal interface material has a thermal conductivity between about 10 W/m·K to about 50 W/m·K.