IP Library › Granted Patent US 12,199,085
Granted Patent B2
US 12,199,085 · App. 17/716,934 · Granted Jan 14, 2025

Multi-chip packaging

Inventors: Robert L. Sankman (Phoenix, AZ); Sairam Agraharam (Chandler, AZ); Shengquan Ou (Chandler, AZ); Thomas J De Bonis (Tempe, AZ); Todd Spencer (Chandler, AZ); Yang Sun (Chandler, AZ); Guotao Wang (Chandler, AZ)
Assignee: Intel Corporation
H01L25/50H01L21/563H01L23/5381H01L23/5385H01L24/06H01L24/11H01L24/16H01L24/17H01L25/18H01L2224/0603H01L2224/11013H01L2224/16145H01L2224/16227H01L2224/16238H01L2224/1703H01L2224/17051
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,199,085
App. No.
17/716,934
Granted
Jan 14, 2025
Kind
B2
Abstract

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Claims (49)

1. A multi-chip package, comprising:

a bridge interconnect in a molding material, the bridge interconnect comprising a first plurality of bridge contacts and a second plurality of bridge contacts, and the bridge interconnect having a bottommost surface;

a first die via and a second die via in the molding material, the first die via and the second die via laterally adjacent to a first side of the bridge interconnect, and the first die via and the second die via each having a bottommost surface co-planar with the bottommost surface of the bridge interconnect;

a third die via and a fourth die via in the molding material, the third die via and the fourth die via laterally adjacent to a second side of the bridge interconnect, the second side opposite the first side, and the third die via and the fourth die via each having a bottommost surface co-planar with the bottommost surface of the bridge interconnect;

a first die electrically coupled to the first plurality of bridge contacts of the bridge interconnect, and the first die electrically coupled to the first die via and to the second die via;

a second die electrically coupled to the second plurality of bridge contacts of the bridge interconnect, and the second die electrically coupled to the third die via and to the fourth die via;

a plurality of solder balls below molding material;

an underfill material laterally surrounding the plurality of solder balls and along sides of the molding material, wherein the underfill material has an uppermost surface below a bottommost surface of a semiconductor material of the first die or the second die;

a substrate having a top surface opposite a bottom surface, the top surface coupled to the plurality of solder balls; and

a plurality of interconnects coupled to the bottom of the substrate.

2. The multi-chip package of claim 1 , wherein the bridge interconnect is in direct contact with the molding material.

3. The multi-chip package of claim 1 , wherein the first die via, the second die via, the third die via, and the fourth die via are in direct contact with the molding material.

4. The multi-chip package of claim 1 , wherein the bridge interconnect is in direct contact with the molding material, and wherein the first die via, the second die via, the third die via, and the fourth die via are in direct contact with the molding material.

5. The multi-chip package of claim 1 , wherein the molding material has a bottommost surface co-planar with the bottommost surface of the bridge interconnect.

6. The multi-chip package of claim 1 , further comprising:

a second bridge interconnect in the molding material, wherein one of the first die or the second die is coupled to the second bridge interconnect; and

a third die electrically coupled to the second bridge interconnect.

7. The multi-chip package of claim 1 , further comprising:

a substrate beneath the molding material; and

the underfill material between the molding material and the substrate.

8. The multi-chip package of claim 1 , wherein the underfill material is further along a side of the molding material.

9. The multi-chip package of claim 1 , wherein the bridge interconnect further comprises a bridge via.

10. The multi-chip package of claim 9 , wherein the bridge via is a through silicon via.

11. The multi-chip package of claim 1 , wherein the first die via, the second die via, the third die via, and the fourth die via extend above the bridge interconnect.

12. The multi-chip package of claim 1 , wherein the molding material is further laterally between the first die and the second die.

13. A multi-chip package, comprising:

a bridge interconnect in a molding material, the bridge interconnect comprising a first plurality of bridge contacts and a second plurality of bridge contacts on an uppermost surface, and the bridge interconnect having a third plurality of bridge contacts on a bottommost surface;

a first die via and a second die via in the molding material, the first die via and the second die via laterally adjacent to a first side of the bridge interconnect;

a third die via and a fourth die via in the molding material, the third die via and the fourth die via laterally adjacent to a second side of the bridge interconnect, the second side opposite the first side;

a first die electrically coupled to the first plurality of bridge contacts of the bridge interconnect, and the first die electrically coupled to the first die via and to the second die via;

a second die electrically coupled to the second plurality of bridge contacts of the bridge interconnect, and the second die electrically coupled to the third die via and to the fourth die via;

a plurality of solder balls below molding material;

an underfill material laterally surrounding the plurality of solder balls and along sides of the molding material, wherein the underfill material has an uppermost surface below a bottommost surface of a semiconductor material of the first die or the second die;

a substrate having a top surface opposite a bottom surface, the top surface coupled to the plurality of solder balls; and

a plurality of interconnects coupled to the bottom of the substrate.

14. The multi-chip package of claim 13 , wherein the bridge interconnect is in direct contact with the molding material.

15. The multi-chip package of claim 13 , wherein the first die via, the second die via, the third die via, and the fourth die via are in direct contact with the molding material.

16. The multi-chip package of claim 13 , wherein the bridge interconnect is in direct contact with the molding material, and wherein the first die via, the second die via, the third die via, and the fourth die via are in direct contact with the molding material.

17. The multi-chip package of claim 13 , further comprising:

a second bridge interconnect in the molding material, wherein one of the first die or the second die is coupled to the second bridge interconnect; and

a third die electrically coupled to the second bridge interconnect.

18. The multi-chip package of claim 13 , further comprising:

a substrate beneath the molding material; and

the underfill material between the molding material and the substrate.

19. The multi-chip package of claim 13 , wherein the underfill material is further along a side of the molding material.

20. The multi-chip package of claim 13 , wherein the bridge interconnect further comprises a bridge via.

21. The multi-chip package of claim 20 , wherein the bridge via is a through silicon via.

22. The multi-chip package of claim 13 , wherein the first die via, the second die via, the third die via, and the fourth die via extend above the bridge interconnect.

23. The multi-chip package of claim 13 , wherein the molding material is further laterally between the first die and the second die.

Continuity (4)
Continuation 17587657 · Jan 28, 2022
Continuation 16892698 · Jun 4, 2020
Continuation 15996870 · Jun 4, 2018
Related Publication 20220231007A1 · Jul 21, 2022
References Cited (51)
US 9653428B1 · Hiner · 2017 [cited by applicant]
US 10700051B2 · Sankman et al. · 2020 [cited by applicant]
US 11469206B2 · Elsherbini · 2022 [cited by applicant]
US 20060226527A1 · Hatano · 2006 [cited by applicant]
US 20130168854A1 · Karikalan · 2013 [cited by applicant]
US 20130200511A1 · Banijamali · 2013 [cited by applicant]
US 20150364422A1 · Zhai et al. · 2015 [cited by applicant]
US 20160133571A1 · Lee et al. · 2016 [cited by applicant]
US 20160343685A1 · Lin · 2016 [cited by applicant]
US 20170110407A1 · Chaware · 2017 [cited by applicant]
US 20170125379A1 · Chen · 2017 [cited by examiner]
US 20170271307A1 · Hiner · 2017 [cited by examiner]
US 20170365580A1 · Shih et al. · 2017 [cited by applicant]
US 20190051633A1 · Bhagavat et al. · 2019 [cited by applicant]
US 20190341368A1 · Hu · 2019 [cited by examiner]
US 20190371778A1 · Sankman et al. · 2019 [cited by applicant]
CN 101232004 · 2008 [cited by applicant]
CN 111886693 · 2020 [cited by applicant]
EP 3111475 · 2017 [cited by applicant]
KR 1020130076749 · 2013 [cited by applicant]
KR 20170126506 · 2017 [cited by applicant]
KR 1020230011436 · 2023 [cited by applicant]
TW 201719843A · 2017 [cited by applicant]
TW 201735276A · 2017 [cited by applicant]
TW 202011559 · 2020 [cited by applicant]
WO WO2016179159 · 2016 [cited by applicant]
WO WO2017099788 · 2017 [cited by applicant]
WO WO2018009145 · 2018 [cited by applicant]
WO WO2019236226 · 2019 [cited by applicant]
Notice of Allowance for Taiwan Patent Application No. 108114442 mailed Mar. 20, 2023, 3 pgs. [cited by applicant]
Office Action from U.S. Appl. No. 17/587,657, mailed Jan. 4, 2023, 10 pgs. [cited by applicant]
Search Report from European Patent Application No. 19814378.6 mailed May 31, 2022, 2022, 36 pgs. [cited by applicant]
International Search Report and Written Opinion for International Patent Application PCT/US2019/030614 mailed Sep. 20, 2019, 10 pgs. [cited by applicant]
International Preliminary Report on Patentability for International Patent Application PCT/US2019/030614 mailed Dec. 17, 2020, 9 pgs. [cited by applicant]
Partial Supplementary ESR for European Patent Application No. 19814378.6 mailed Jan. 24, 2022, 39 pgs. [cited by applicant]
Extended European Search Report for European Patent Application No. 22171597.2 mailed Oct. 17, 2022, 14 pgs. [cited by applicant]
Office Action for Taiwan Patent Application No. 108114442 mailed Aug. 17, 2022, 14 pgs., with English translation. [cited by applicant]
Extended European Search Report for European Patent Application No. 21210501.9 mailed Jun. 22, 2022, 12 pgs. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/587,657 mailed Jul. 17, 2023, 8 pgs. [cited by applicant]
Office Action for Taiwan Patent Application No. 111115241 mailed Apr. 21, 2023, 6 pgs. [cited by applicant]
Notice of Allowance for Taiwan Patent Application No. 112119616 mailed Nov. 17, 2023, 3 pgs. [cited by applicant]
Search Report for European Patent No. 23176064.6 mailed Jan. 24, 2024, 104 pgs. [cited by applicant]
Notice of Allowance for Taiwan Patent Application No. 111115241 mailed Sep. 5, 2023, 3 pgs. [cited by applicant]
Office Action from Korean Patent Application No. 10-2020-7027577, mailed Oct. 12, 2023, 17 pgs. [cited by applicant]
Office Action from Korean Patent Application No. 10-2022-7013121 mailed Oct. 13, 2023, 8 pgs. [cited by applicant]
Extended European Search Report for European Patent Application No. 23219820.0 mailed Jun. 12, 2024, 17 pgs. [cited by applicant]
Notice of Allowance from Korean Patent Application No. 10-2020-7027577 mailed Jun. 6, 2024, 4 pgs. [cited by applicant]
Final Office Action from Korean Patent Application No. 10-2022-7013121 mailed May 28, 2024, 10 pgs. [cited by applicant]
Office Action from Korean Patent Application No. 10-2023-7042877, mailed Mar. 29, 2024, 22 pgs. [cited by applicant]
Notice of Allowance for Taiwan Patent Application No. 112151263 mailed Feb. 1, 2024, 5 pgs. [cited by applicant]
Notice of Allowance from Korean Patent Application No. 10-2022-7013121 mailed Sep. 2, 2024, 4 pgs. [cited by applicant]