Neuromorphic device and electronic device including the same
A neuromorphic device includes a plurality of cell tiles including a cell array including a plurality of memory cells storing a weight of a neural network, a row driver connected to the plurality of memory cells, and cell analog-digital converters connected to the plurality of memory cells and converting cell currents into a plurality of pieces of digital cell data, a reference tile including a plurality of reference cells, a reference row driver connected to the plurality of reference cells, and reference analog-digital converters connected to the plurality of reference cells and converting reference currents read via the plurality of reference column lines into a plurality of pieces of digital reference data, and a comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data, respectively.
1 . A neuromorphic device, comprising:
a plurality of cell tiles, each of the plurality of cell tiles including:
a cell array including a plurality of memory cells configured to store weights of a neural network,
a row driver connected to the plurality of memory cells via a plurality of row lines, and
at least one cell analog-digital converter (ADC) connected to the plurality of memory cells via a plurality of column lines, the at least one cell ADC configured to convert cell currents read via the plurality of column lines into a plurality of pieces of digital cell data;
a reference tile distinct from the plurality of cell tiles, the reference tile including:
a reference cell array including a plurality of reference cells, the reference cell array distinct from the cell array of each of the plurality of cell tiles,
a reference row driver connected to the plurality of reference cells via a plurality of reference row lines, the reference row driver distinct from the row driver connected to the plurality of memory cells, and
at least one reference ADC connected to the plurality of reference cells via a plurality of reference column lines, the at least one reference ADC configured to convert reference currents read via the plurality of reference column lines into a plurality of pieces of digital reference data, wherein the at least one reference ADC is distinct from the at least one ADC connected to the plurality of memory cells; and
at least one comparator circuit configured to compare the plurality of pieces of digital cell data with the plurality of pieces of digital reference data.
2 . The neuromorphic device of claim 1 , wherein the reference tile further includes:
a buffer configured to store the plurality of pieces of digital reference data output by the at least one reference ADC.
3 . The neuromorphic device of claim 1 , wherein the neuromorphic device is configured such that, when an inference using the neural network starts,
the reference tile converts the reference currents into the plurality of pieces of digital reference data and stores the data in a buffer, and
the at least one comparator circuit compares the plurality of pieces of digital cell data output by each of the plurality of cell tiles with the plurality of pieces of digital reference data stored in the buffer.
4 . The neuromorphic device of claim 1 , wherein:
the at least one comparator circuit includes a plurality of comparator circuits, each of the plurality of comparator circuits including a plurality of comparators, respectively, and the plurality of comparator circuits are connected to the plurality of cell tiles, respectively, and
a number of the plurality of comparators included in the plurality of comparator circuits is equal to a number of the plurality of column lines included in the plurality of cell tiles.
5 . The neuromorphic device of claim 1 , wherein the at least one comparator circuit includes a plurality of comparators, and the plurality of comparators are connected to the plurality of cell tiles, respectively.
6 . The neuromorphic device of claim 1 , wherein:
the at least one comparator circuit includes a plurality of comparator circuits having a plurality of comparators, respectively,
each of the plurality of comparator circuits is connected to two or more cell tiles of the plurality of cell tiles, and
the two or more cell tiles are configured to store weights included in a single layer among a plurality of layers included in the neural network.
7 . The neuromorphic device of claim 1 , wherein the comparator circuit includes a plurality of comparators, and each of the plurality of comparators is connected to two or more of the plurality of cell tiles.