Semiconductor device and method of fabricating the same
A semiconductor memory device includes active sections that include first and second impurity regions and are defined by a device isolation layer. Word lines extend in a first direction on the active sections. Intermediate dielectric patterns cover top surfaces of the word lines. Bit-line structures extend on the word lines in a second direction intersecting the first direction. Contact plugs are disposed between the bit-line structures and are connected to the second impurity regions. Data storage elements are disposed on the contact plugs. The intermediate dielectric pattern includes a capping part that covers the top surfaces of the word lines and is buried in the substrate. Fence parts extend between the bit-line structures from the capping part.
1 . A semiconductor memory device, comprising:
a plurality of active sections disposed on a substrate, the plurality of active sections includes a plurality of first impurity regions and a plurality of second impurity regions, each of the plurality of active sections being defined by a device isolation layer;
a plurality of word lines that extend in a first direction, over the plurality of active sections;
a plurality of intermediate dielectric patterns that correspondingly cover top surfaces of the plurality of word lines;
a plurality of bit-line structures that extend in a second direction, over the plurality of word lines, the second direction intersecting the first direction;
a plurality of contact plugs disposed between the plurality of bit-line structures and connected to corresponding second impurity regions of the plurality of second impurity regions; and
a plurality of data storage elements disposed on corresponding contact plugs of the plurality of contact plugs,
wherein each of the plurality of intermediate dielectric patterns has a single-body structure that includes:
a cap that covers the top surfaces of the plurality of word lines and is buried within the substrate; and
a plurality of fences that extend between the plurality of bit-line structures from the cap,
wherein each of the plurality of fences includes a first portion between the contact plugs, the first portion has a first width in the second direction between the contact plugs,
wherein the cap includes a second portion below the first portion, the second portion has a second width in the second direction,
wherein the first width is less than the second width.
2 . The device of claim 1 , wherein the plurality of contact plugs are disposed in areas defined by the plurality of fences and the plurality of bit-line structures.
3 . The device of claim 1 , further comprising a plurality of spacers disposed between the plurality of contact plugs and the plurality of bit-line structures,
wherein the plurality of spacers extend between the plurality of fences and the plurality of bit-line structures.
4 . The device of claim 1 , wherein top surfaces of the plurality of fences are higher than top surfaces of the plurality of bit-line structures.
5 . The device of claim 1 , wherein each of the plurality of bit-line structures includes:
a plurality of contacts buried in an upper portion of the substrate and connected to corresponding first impurity regions of the plurality of first impurity regions; and
a line that extends in the second direction and is connected in common to the plurality of contacts.
6 . The device of claim 5 , wherein the plurality of contacts and the line are portions of a single layer that is formed of a same material.
7 . The device of claim 5 , further comprising a plurality of spacers that cover sidewalls of the plurality of bit-line structures,
wherein each of the plurality of spacers includes:
a first section that covers a first sidewall of one of the plurality of bit-line structures;
a second section that covers a second sidewall of the one of the plurality of bit-line structures, the second sidewall being opposite to the first sidewall; and
a third section that covers sidewalls of the plurality of contacts below the line and connects the first section and the second section to each other.
8 . The device of claim 5 , further comprising a plurality of spacers that cover sidewalls of the plurality of bit-line structures,
wherein bottom surfaces of the plurality of contacts are lower than bottom surfaces of the plurality of spacers.
9 . The device of claim 5 , wherein a width in the first direction at a top surface of the line is greater than a width in the first direction at a bottom surface of one of the plurality of contacts.
10 . A semiconductor memory device, comprising:
a plurality of active sections disposed on a substrate, the plurality of active sections includes a plurality of first impurity regions and a plurality of second impurity regions, each of the plurality of active sections being defined by a device isolation layer;
a plurality of word lines that extend in a first direction, over the plurality of active sections;
a plurality of bit-line structures disposed on the plurality of word lines, each of the plurality of bit-line structures extending in a second direction, the second direction intersecting the first direction;
a plurality of contact plugs disposed between the plurality of bit-line structures and connected to corresponding second impurity regions of the plurality of second impurity regions;
a plurality of intermediate dielectric patterns that correspondingly cover top surfaces of the plurality of word lines, wherein each of the plurality of intermediate dielectric patterns has a single-body structure that includes a plurality of fences extends beyond the plurality of bit-line structures in a first cross-section parallel to the first direction, beyond the plurality of contact plugs in a second cross-section parallel to the second direction, or both;
a plurality of spacers disposed between the plurality of contact plugs and the plurality of bit-line structures; and
a plurality of data storage elements disposed on corresponding contact plugs of the plurality of contact plugs,
wherein each of the plurality of bit-line structures includes:
a plurality of contacts buried in an upper portion of the substrate and connected to corresponding first impurity regions of the plurality of first impurity regions; and
a line that extends in the second direction and is connected in common to the plurality of contacts,
wherein a bottom surface of at least one of the plurality of contacts is at a level that is lower than levels of bottom surfaces of the plurality of spacers.
11 . The device of claim 10 , wherein the plurality of contacts and the line are portions of a single layer that is formed of a same material.
12 . The device of claim 10 , further comprising a metal silicide layer disposed between the plurality of contacts and the plurality of first impurity regions.
13 . The device of claim 10 , further comprising a conductive metal nitride layer disposed between the plurality of contacts and the plurality of first impurity regions.
14 . The device of claim 10 , wherein each of the plurality of spacers includes:
a first section that covers a first sidewall of one of the plurality of bit-line structures;
a second section that covers a second sidewall of the one of the plurality of bit-line structures, the second sidewall being opposite to the first sidewall; and
a third section that covers sidewalls of the plurality of contacts below the line and connects the first section and the second section to each other.
15 . The device of claim 10 , wherein a width in the first direction at a top surface of the line is greater than a width in the first direction at a bottom surface of one of the plurality of contacts.
16 . The device of claim 10 , further comprising a plurality of intermediate dielectric patterns that correspondingly cover top surfaces of the plurality of word lines,
wherein each of the plurality of intermediate dielectric patterns further includes:
a cap that covers the top surfaces of the plurality of word lines and is buried in the substrate,
wherein the plurality of fences extend between the plurality of bit-line structures, from the cap.
17 . The device of claim 16 , wherein a width in the second direction of each of the plurality of fences is less than a width in the second direction of the cap.
18 . The device of claim 16 , wherein the cap and the plurality of fences are portions of a single layer that is formed of a same material.
19 . A semiconductor memory device, comprising:
a plurality of active sections disposed on a substrate, the plurality of active sections including a plurality of first impurity regions and a plurality of second impurity regions, the plurality of active sections being defined by a device isolation layer;
a plurality of word lines that extend in a first direction on the plurality of active sections;
a gate dielectric layer disposed between the plurality of word lines and the plurality of active sections;
a plurality of intermediate dielectric patterns that correspondingly cover top surfaces of the plurality of word lines;
a plurality of bit-line structures that extend in a second direction on the plurality of word lines, the second direction intersecting the first direction;
a plurality of contact plugs disposed between the plurality of bit-line structures and connected to corresponding second impurity regions of the plurality of second impurity regions;
a plurality of landing pads disposed on the plurality of contact plugs;
a gap-fill structure that fills a space between landing pads of the plurality of landing pads; and
a capacitor connected to the plurality of second impurity regions through the plurality of contact plugs and the plurality of landing pads,
wherein each of the plurality of intermediate dielectric patterns has a single-body structure that includes:
a cap that covers the top surfaces of the plurality of word lines and is buried in the substrate; and
a plurality of fences that extend between the plurality of bit-line structures, from the cap, wherein the plurality of fences extends beyond the plurality of bit-line structures in a first cross-section parallel to the first direction, beyond the plurality of contact plugs in a second cross-section parallel to the second direction, or both.