Semiconductor device having recessed landing pad and its method of fabrication
A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.
1. A semiconductor device, comprising:
a semiconductor substrate;
a lower interlayer dielectric layer disposed on the semiconductor substrate;
a first landing pad contacting the semiconductor substrate through the lower interlayer dielectric layer;
a second landing pad contacting the semiconductor substrate through the lower interlayer dielectric layer, and spaced apart from the first landing pad;
a metal silicide layer formed on the second landing pad and disposed lower than a top surface of the first landing pad;
an intermediate interlayer dielectric layer disposed on the lower interlayer dielectric layer;
a conductive line disposed on the intermediate interlayer dielectric layer; and
a contact plug disposed between the conductive line and the metal silicide layer, wherein an upper end of the metal silicide layer is located below the top surface of the first landing pad.
2. The semiconductor device according to claim 1 , further comprising:
a plug spacer surrounding sidewalls of the contact plug,
wherein the plug spacer penetrates the intermediate interlayer dielectric layer along the sidewalls of the contact plug to extend into the lower interlayer dielectric layer.
3. The semiconductor device according to claim 2 , wherein the plug spacer is a material layer having an etch selectivity with respect to the intermediate interlayer dielectric layer and the lower interlayer dielectric layer.
4. The semiconductor device according to claim 2 , wherein the metal silicide layer is disposed below the plug spacer.
5. The semiconductor device according to claim 1 , wherein the contact plug includes:
an upper plug penetrating the intermediate interlayer dielectric layer; and
a lower plug extending below the upper plug and disposed in the lower interlayer dielectric layer, and having a width larger than the upper plug.
6. The semiconductor device according to claim 5 , wherein the lower plug has a substantially spherical shape.
7. The semiconductor device according to claim 5 , further comprising:
a barrier metal layer surrounding sidewalls of the upper plug and sidewalls and a bottom surface of the lower plug.
8. The semiconductor device according to claim 1 , wherein the metal silicide layer is a material selected from the group consisting of WSi, TiSi, NiSi, MoSi, ZrSi, PtSi, IrSi, and TaSi.
9. The semiconductor device according to claim 1 , further comprising:
an upper interlayer dielectric layer covering the conductive line and the intermediate interlayer dielectric layer;
a storage node disposed on the upper interlayer dielectric layer; and
a node contact plug disposed between the first landing pad and the storage node.
10. The semiconductor device according to claim 9 , further comprising:
a node contact spacer surrounding sidewalls of the node contact plug,
wherein the node contact spacer is an insulating material layer.
11. A semiconductor device, comprising:
a semiconductor substrate;
an interlayer dielectric layer disposed on the semiconductor substrate;
a first landing pad contacting the semiconductor substrate through the interlayer dielectric layer;
a second landing pad contacting the semiconductor substrate through the interlayer dielectric layer, the second landing pad spaced apart from the first landing pad;
a metal silicide layer formed on the second landing pad and disposed lower than a top surface of the first landing pad;
a conductive line disposed on the interlayer dielectric layer; and
a contact plug disposed between the conductive line and the metal silicide layer, wherein an upper end of the metal silicide layer is located below the top surface of the first landing pad.