Semiconductor die assembly having a polygonal linking die
A semiconductor die assembly is provided. The semiconductor die assembly includes: a first bottom die and a second bottom die disposed at a bottom vertical level; a first top die disposed at a top vertical level above the bottom vertical level in a vertical direction and bonded to the first bottom die; a second top die disposed at the top vertical level and bonded to the second bottom die; and a linking die disposed at the top vertical level and bonded to both the first bottom die and the second bottom die. The linking die is characterized by a polygonal shape in a horizontal plane perpendicular to the vertical direction, and the polygonal shape is not a rectangle.
1 . A semiconductor die assembly comprising:
a first bottom die and a second bottom die disposed at a bottom vertical level;
a first top die disposed at a top vertical level above the bottom vertical level in a vertical direction and bonded to the first bottom die;
a second top die disposed at the top vertical level and bonded to the second bottom die; and
a linking die disposed at the top vertical level and bonded to both the first bottom die and the second bottom die, wherein the linking die is characterized by a polygonal shape in a horizontal plane perpendicular to the vertical direction, and the polygonal shape is not a rectangle, and the polygonal shape is determined such that a nonoverlapping area at the top vertical level is minimized.
2 . The semiconductor die assembly of claim 1 , wherein the first top die is bonded to the first bottom die using hybrid bonding, the second top die is bonded to the second bottom die using hybrid bonding, the linking die is bonded to both the first bottom die and the second bottom die using hybrid bonding.
3 . The semiconductor die assembly of claim 1 , wherein the linking die comprises a multilayer interconnect structure.
4 . The semiconductor die assembly of claim 3 , wherein the linking die further comprises semiconductor devices.
5 . The semiconductor die assembly of claim 1 , wherein the polygonal shape is a “T” shape.
6 . The semiconductor die assembly of claim 1 , wherein the polygonal shape is a “cross” shape.
7 . The semiconductor die assembly of claim 1 , wherein the polygonal shape is an “H” shape.
8 . The semiconductor die assembly of claim 1 , wherein the linking die is separated using plasma dicing.
9 . The semiconductor die assembly of claim 1 , further comprising:
a third top die disposed at the top vertical level and bonded to the first bottom die; and
a fourth top die disposed at the top vertical level and bonded to the second bottom die.
10 . The semiconductor die assembly of claim 1 , wherein a first bonding layer at a bottom surface of the linking die is bonded to a second bonding layer at a top surface of the first bottom die, a first hybrid bonding metal pad disposed in the first bonding layer is bonded to a second hybrid bonding metal pad disposed in the second bonding layer.
11 . A method for fabricating a semiconductor die assembly comprising:
placing a first bottom die and a second bottom die at a bottom vertical level;
bonding a first top die to the first bottom die using hybrid bonding, the first top die being at a top vertical level above the bottom vertical level in a vertical direction;
bonding a second top die to the second bottom die, the second top die being at the top vertical level;
forming a linking die, the linking die being characterized by a polygonal shape in a horizontal plane perpendicular to the vertical direction, and the polygonal shape is not a rectangle, and the polygonal shape is determined such that a nonoverlapping area at the top vertical level is minimized; and
bonding the linking die to both the first bottom die and the second bottom die, the linking die being at the top vertical level.
12 . The method of claim 11 , wherein the forming the linking die comprises:
fabricating the linking die on a wafer;
performing a plasma dicing process to define boundaries of the linking die; and
performing a backside grinding process to separate the linking die.
13 . The method of claim 11 , further comprising:
determining the polygonal shape based at least on geometries of the first top die and the second top die.
14 . A semiconductor package comprising:
a package substrate;
a semiconductor die assembly disposed over and electrically connected to the package substrate, wherein the semiconductor die assembly comprises:
a first bottom die and a second bottom die disposed at a bottom vertical level;
a first top die disposed at a top vertical level above the bottom vertical level in a vertical direction and bonded to the first bottom die;
a second top die disposed at the top vertical level and bonded to the second bottom die; and
a linking die disposed at the top vertical level and bonded to both the first bottom die and the second bottom die, wherein the linking die is characterized by a polygonal shape in a horizontal plane perpendicular to the vertical direction, and the polygonal shape is not a rectangle, and the polygonal shape is determined such that a nonoverlapping area at the top vertical level is minimized.
15 . The semiconductor package of claim 14 , wherein the first top die is bonded to the first bottom die using hybrid bonding, the second top die is bonded to the second bottom die using hybrid bonding, the linking die is bonded to both the first bottom die and the second bottom die using hybrid bonding.
16 . The semiconductor package of claim 14 , wherein the first bottom die and the second bottom die are bonded to the package substrate.
17 . The semiconductor package of claim 16 , wherein a local silicon interconnect (LSI) chip is embedded in the package substrate, and the LSI chip is electrically connected to both the first bottom die and the second bottom die.
18 . The semiconductor package of claim 14 , further comprising:
a silicon chip disposed between the semiconductor die assembly and the package substrate in the vertical direction, wherein the silicon chip is bonded to the first bottom die and the second bottom die using hybrid bonding, and the silicon chip is bonded to the package substrate.
19 . The semiconductor package of claim 14 , further comprising:
a silicon chip disposed between the semiconductor die assembly and the package substrate in the vertical direction, wherein the silicon chip is bonded to the first bottom die and the second bottom die through micro-bumps, and the silicon chip is bonded to the package substrate.
20 . The semiconductor die assembly of claim 10 , wherein the first bonding layer at the bottom surface of the linking die is bonded to a third bonding layer at a top surface of the second bottom die, a third hybrid bonding metal pad disposed in the first bonding layer is bonded to a fourth hybrid bonding metal pad disposed in the third bonding layer.