Methods and apparatus for a novel memory array
Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.
1. A method for reading a dynamic random-access memory (DRAM) array having memory cells connected to a plurality of bit lines that are connected to a single sense amplifier through a plurality of bit line select gates, respectively, the method comprising:
activating the bit line select gates to equalize voltage levels on the plurality of bit lines;
deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line;
activating a selected word line to access selected memory cells connected to the selected word line;
activating bit line select gates associated with selected bit lines to pass first data from a first bit line and second data from a second bit line to the sense amplifier, wherein the first data is from a selected memory cell and the second data is reference data; and
determining sensed data from the first and second data, wherein the sensed data is passed from the sense amplifier onto an I/O bus.
2. The method of claim 1 , further comprising:
maintaining voltage on the selected word line; and
writing data on the bit lines back to the selected cells in a restore operation.
3. The method of claim 1 , further comprising an operation of activating bit line select gates of unselected bit lines to restore data to memory cells associated with the unselected bit lines.
4. The method of claim 3 , further comprising activating the bit line select gates of unselected bit lines in a sequential manner.
5. The method of claim 3 , further comprising activating the bit line select gates of unselected bit lines in a non-sequential manner.
6. The method of claim 1 , wherein the equalized voltage levels on the plurality of bit lines are approximately equal to (½*VDD).
7. The method of claim 1 , wherein the operation of activating bit line select gates associated with selected bit lines causes charge-sharing with the selected cells' capacitors that are storing VDD and VSS.
8. The method of claim 7 , wherein bit lines associated with cells having capacitors storing VDD levels will have a charge-sharing values greater than (½*VDD), and bit lines associated with cells having capacitors storing VSS levels will have a charge-sharing values less than (½*VDD).
9. The method of claim 1 , further comprising controlling column select gates to enable the sensed data to pass onto the I/O bus.