3D source and drain contacts tuned for vertically stacked PMOS and NMOS
An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.
1 . An integrated circuit, comprising:
a vertical stack of devices comprising a first device, and a second device above the first device,
wherein the first device comprises (i) a first source region, (ii) a first drain region, (iii) a first body comprising semiconductor material laterally extending from the first source region to the first drain region, (iv) a first source contact coupled to the first source region, the first source contact comprising a first conductive material, and (v) a first drain contact coupled to the first drain region, the first drain contact comprising the first conductive material, and
wherein the second device comprises (i) a second source region, (ii) a second drain region, (iii) a second body comprising semiconductor material laterally extending from the second source region to the second drain region, (iv) a second source contact coupled to the second source region, the second source contact comprising a second conductive material, and (V a second drain contact coupled to the second drain region, the second drain contact comprising the second conductive material,
wherein the first conductive material is only a single metal that is elementally different from any metal of the second conductive material, or the first conductive material is a metal alloy that is elementally different from the second conductive material, and wherein a top surface of the first drain contact is in contact with a bottom surface of the second drain contact.
2 . The integrated circuit of claim 1 , wherein the first device is a p-channel metal-oxide semiconductor (PMOS) device and the first conductive material comprises one or both of tungsten and cobalt.
3 . The integrated circuit of claim 1 , wherein the second device is a n-channel metal-oxide semiconductor (NMOS) device and the second conductive material comprises molybdenum.
4 . The integrated circuit of claim 1 , wherein one of the first or second conductive material comprises one or both of tungsten and cobalt, and wherein the other of the first or second conductive material comprises molybdenum.
5 . The integrated circuit of claim 1 , wherein the first conductive material induces one of compressive strain or tensile strain on the first body of the first device, and the second conductive material induces the other of compressive strain or tensile strain on the second body of the second device.
6 . The integrated circuit of claim 1 , wherein the first conductive material induces compressive strain on the first body of the first device, and the second conductive material induces tensile strain on the second body of the second device.
7 . The integrated circuit of claim 1 , wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.
8 . The integrated circuit of claim 1 , wherein the first source contact extends within the first source region, and wherein first drain contact extends within the first drain region.
9 . The integrated circuit of claim 1 , wherein the first source contact extends within and through the first source region, such that a bottom surface of the first source contact and a bottom surface of the first source region are coplanar.
10 . The integrated circuit of claim 1 , further comprising:
an isolation region between the first source region and the second source region, wherein the first source contact extends within and through the first source region, such that a bottom surface of the first source contact is in contact with the isolation region.
11 . The integrated circuit of claim 10 , wherein a top surface of the first source contact is in contact with a bottom surface of the second source contact.
12 . An integrated circuit structure comprising:
a first transistor device comprising a first source or drain contact coupled to a first source or drain region and a second source or drain contact coupled to a second source or drain region,
the first source or drain contact and the second source or drain contact each consisting of tungsten or cobalt; and
a second transistor device comprising a third source or drain contact coupled to a third source or drain region and a fourth source or drain contact coupled to a fourth source or drain region, the third source or drain contact and the fourth source or drain contact each consisting of molybdenum,
wherein the first device and the second device are arranged in a vertical device stack.
13 . The integrated circuit structure of claim 12 , wherein the second device is above the first device in the vertical device stack.
14 . The integrated circuit structure of claim 12 , wherein a surface of the first source or drain contact is in contact with a surface of the second source or drain contact.
15 . The integrated circuit structure of claim 12 , wherein the first transistor device is a p-type MOS (PMOS) device, and the second transistor device is an n-type MOS (NMOS) device.
16 . An integrated circuit, comprising:
a first device comprising (i) a first source region, (ii) a first drain region, (iii) a first nanoribbon laterally extending from the first source region to the first drain region, (iv) a first source contact extending within the first source region, and (v) a first drain contact extending within the first drain region; and
a second device comprising (i) a second source region, (ii) a second drain region, (iii) a second nanoribbon laterally extending from the second source region to the second drain region, (iv) a second source contact extending within the second source region, and (v) a second drain contact extending within the second drain region,
wherein the first device and the second device are arranged in a vertical device stack,
wherein the first source contact and the first drain contact comprise a first conductive material that induces compressive strain within the first nanoribbon, and the second source contact and the second drain contact comprise a second conductive material that induces tensile strain within the second nanoribbon, wherein the first conductive material consists of tungsten or cobalt, and the second conductive material consists of molybdenum.
17 . The integrated circuit of claim 16 , wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.
18 . The integrated circuit of claim 1 , wherein the first conductive material consists of tungsten or cobalt, and the second conductive material consists of molybdenum.
19 . The integrated circuit of claim 16 , wherein a top surface of the first drain contact is in contact with a bottom surface of the second drain contact.
20 . The integrated circuit structure of claim 12 , wherein a top surface of the first source or drain contact is in contact with a bottom surface of the third source or drain contact.