3D source and drain contacts tuned for PMOS and NMOS
An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device. The first device includes (i) a first source region, and a first source contact including a first conductive material, (ii) a first drain region, and a first drain contact including the first conductive material, and (iii) a first body laterally between the first source region and the first drain region. The second device includes (i) a second source region, and a second source contact including a second conductive material, (ii) a second drain region, and a second drain contact including the second conductive material, and (iii) a second body laterally between the second source region and the second drain region. The first and second conductive materials are compositionally different. The first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.
1 . An integrated circuit, comprising:
a first device comprising (i) a first source region, (ii) a first drain region, (iii) a first body comprising semiconductor material laterally extending from the first source region to the first drain region, (iv) a first source contact coupled to the first source region, the first source contact comprising a first conductive material, and (v) a first drain contact coupled to the first drain region, the first drain contact comprising the first conductive material; and
a second device laterally adjacent to the first device, the second device comprising (i) a second source region, (ii) a second drain region, (iii) a second body comprising semiconductor material laterally extending from the second source region to the second drain region, (iv) a second source contact coupled to the second source region, the second source contact comprising a second conductive material, and (v) a second drain contact coupled to the second drain region, the second drain contact comprising the second conductive material,
wherein the first conductive material consists of tungsten or cobalt, and the second conductive material consists of molybdenum.
2 . The integrated circuit of claim 1 , wherein the first device is a p-channel metal-oxide semiconductor (PMOS) device.
3 . The integrated circuit of claim 1 , wherein the second device is a n-channel metal-oxide semiconductor (NMOS) device.
4 . The integrated circuit of claim 1 , wherein the first conductive material induces compressive strain on the first body of the first device.
5 . The integrated circuit of claim 1 , wherein the second conductive material induces tensile strain on the second body of the second device.
6 . The integrated circuit of claim 1 , wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.
7 . The integrated circuit of claim 1 , wherein the first source contact extends within the first source region, and wherein the first drain contact extends within the first drain region.
8 . The integrated circuit of claim 1 , wherein the first source contact extends within and through the first source region, such that a bottommost surface of the first source contact and a bottommost surface of the first source region are coplanar.
9 . The integrated circuit of claim 1 , wherein the second device is laterally separated from the first device by at most 400 nanometers.
10 . The integrated circuit of claim 1 , wherein the first body comprises a first nanoribbon, and the second body comprises a second nanoribbon.
11 . An integrated circuit comprising:
a first transistor device comprising a first source or drain contact coupled to a first source or drain region and a second source or drain contact coupled to a second source or drain region, the first source or drain contact and the second source or drain contact each comprising an alloy of tungsten and cobalt and not comprising molybdenum; and
a second transistor device laterally adjacent to the first transistor device, the second transistor device comprising a third source or drain contact coupled to a third source or drain region and a fourth source or drain contact coupled to a fourth source or drain region, the third source or drain contact and the fourth source or drain contact each comprising an alloy of molybdenum and not comprising tungsten or cobalt.
12 . The integrated circuit of claim 11 , wherein the first transistor device and the second transistor device are coupled in a complementary metal oxide semiconductor (CMOS) architecture.
13 . The integrated circuit of claim 11 , wherein the first transistor device is a p-type MOS (PMOS) device, and the second transistor device is an n-type MOS (NMOS) device.
14 . An integrated circuit, comprising:
a first device comprising (i) a first source region, (ii) a first drain region, (iii) a first body comprising semiconductor material laterally extending from the first source region to the first drain region, (iv) a first source contact extending within the first source region, and (v) a first drain contact extending within the first drain region; and
a second device comprising (i) a second source region, (ii) a second drain region, (iii) a second body comprising semiconductor material laterally extending from the second source region to the second drain region, (iv) a second source contact extending within the second source region, and (v) a second drain contact extending within the second drain region,
wherein the first source contact and the first drain contact comprise a first conductive material that induces compressive strain within the first body, and the second source contact and the second drain contact comprise a second conductive material that induces tensile strain within the second body, wherein the first conductive material consists of tungsten or cobalt, and the second conductive material consists of molybdenum.
15 . The integrated circuit of claim 14 , wherein a lateral distance between the first source contact and the first body is in the range of 3-12 nm (nanometers), and wherein a lateral distance between the second source contact and the second body is in the range of 3-12 nm.
16 . The integrated circuit of claim 14 , wherein the first device is a p-channel metal-oxide semiconductor (PMOS) device, and the second device is a n-channel metal-oxide semiconductor (NMOS) device.
17 . The integrated circuit of claim 11 , wherein the first source or drain contact extends within and through the first source or drain region, such that a bottommost surface of the first source or drain contact and a bottommost surface of the first source or drain region are coplanar.
18 . The integrated circuit of claim 11 , wherein the second transistor device is laterally separated from the first transistor device by at most 400 nanometers.
19 . The integrated circuit of claim 14 , wherein the first source contact extends through the first source region, such that a bottommost surface of the first source contact and a bottommost surface of the first source region are coplanar.
20 . The integrated circuit of claim 14 , wherein the second device is laterally separated from the first device by at most 400 nanometers.