Compliance and debug testing of a die-to-die interconnect
In one embodiment, an apparatus comprises a first die that includes: a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information of a first interconnect protocol; and the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, where the physical layer circuitry is to receive and output the message information to a second die via an interconnect having a mainband and a sideband. During a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers. Other embodiments are described and claimed.
1. An apparatus comprising:
a first die comprising:
a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to receive message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter, the physical layer circuity comprising a plurality of second registers, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect having a mainband and a sideband, wherein the physical layer circuitry is to
reverse a logical lane order of at least some of a plurality of data lanes of the mainband when a lane reversal with respect to the first die and the second die is detected,
wherein during a test of the apparatus, the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers.
2. The apparatus of claim 1 , wherein the test comprises a compliance test and during the compliance test, the sideband is to send testing information comprising at least one of eye margin testing or voltage sensitivity testing.
3. The apparatus of claim 1 , wherein the test comprises a compliance test and during the compliance test, the sideband is to send training information comprising training of the second die, wherein the training comprises link training state machine training.
4. The apparatus of claim 3 , wherein the plurality of first registers comprises link status and control registers.
5. The apparatus of claim 1 , wherein the first die comprises a reference die that is a known good die and the second die comprises a device under test, the apparatus comprising a test package having the first die and the second die.
6. The apparatus of claim 5 , wherein the test package further comprises a third die comprising another device under test.
7. The apparatus of claim 5 , wherein the test package further comprises:
a known good interposer, the first die and the second die adapted to the known good interposer; and
a substrate to which the known good interposer is adapted.
8. The apparatus of claim 1 , wherein the first die comprises:
a first port comprising the die-to-die adapter and the physical layer circuitry;
a second port comprising a second die-to-die adapter and second physical layer circuitry; and
a mirror port coupled between the first port and the second port.
9. The apparatus of claim 8 , wherein in response to a failure in the first port, the mirror port is to communicate debug information of the first port to a destination via the second port.
10. The apparatus of claim 1 , wherein the interconnect comprises a multi-protocol capable interconnect having a Universal Chiplet Interconnect express (UCIe) architecture, the first interconnect protocol comprising a flit mode of a Peripheral Component Interconnect express (PCIe) protocol and the interconnect further to communicate second information of a second interconnect protocol, the second interconnect protocol comprising a flit mode of a Compute Express Link (CXL) protocol.
11. A method comprising:
performing a first reset of a first die of a test package and a second reset of a second die of the test package, the first die comprising a reference die that is a known good die and the second die comprising a device under test;
after performing the first reset and the second reset, training a sideband of an interconnect that couples the first die and the second die, the interconnect comprising a mainband and the sideband; and
monitoring, using the first die, a progression of at least one link training state machine of the second die as part of a testing of the second die.
12. The method of claim 11 , further comprising:
accessing during the testing, via the sideband, one or more registers of a die-to-die adapter of the second die; and
accessing during the testing, via the sideband, one or more registers of physical layer circuitry of the second die.
13. The method of claim 12 , further comprising accessing the one or more registers of at least one of the die-to-die adapter and the physical layer circuitry via a mirror port coupled between a first port and a second port of the second die, the first port comprising the die-to-die adapter and the physical layer circuitry and the second port comprising a second die-to-die adapter and second physical layer circuitry.
14. The method of claim 11 , wherein monitoring the progression of the at least one link training state machine of the second die comprises:
monitoring a plurality of state progressions of the at least one link training state machine; and
identifying an amount of time spent in each of a plurality of states of the at least one link training state machine.
15. The method of claim 11 , further comprising exercising a plurality of arcs of a flit format negotiation tree as part of the testing, the testing comprising compliance testing.
16. The method of claim 11 , further comprising testing one or more of eye margin, voltage sensitivity, or pattern checking as part of the testing, the testing comprising compliance testing.
17. A package comprising:
a first die comprising a central processing unit (CPU) and a protocol stack comprising:
a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to communicate message information, the message information comprising first information of a first interconnect protocol; and
the physical layer circuitry coupled to the die-to-die adapter via the RDI, the physical layer circuity comprising a plurality of second registers, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect having a mainband and a sideband,
wherein the physical layer circuitry is to perform a link initialization of the interconnect and the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers to monitor a progression of at least one link training state machine of the second die as part of a testing of the second die; and
the second die coupled to the first die via the interconnect, wherein the first die comprises a known good die and the second die comprises a device under test.
18. The package of claim 17 , wherein the package comprises a test package, the test package further comprising:
a third die comprising another device under test;
a known good interposer, at least two of the first die, the second die, or the third die adapted to the known good interposer; and
a substrate to which the known good interposer is adapted.
19. The package of claim 17 , wherein the first die comprises:
a first port comprising the die-to-die adapter and the physical layer circuitry;
a second port comprising a second die-to-die adapter and second physical layer circuitry; and
a mirror port coupled between the first port and the second port, wherein in response to a failure in the first port, the mirror port is to communicate debug information of the first port to a destination via the second port.
20. The package of claim 17 , wherein the second die comprises an accelerator, wherein the first die is to communicate with the second die according to at least one of a flit mode of a Peripheral Component Interconnect express (PCIe) protocol or a flit mode of a Compute Express Link (CXL) protocol.