Metal gates and manufacturing methods thereof
A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.
1 . A method, comprising:
forming an interfacial layer over a substrate;
depositing a high-k dielectric layer over the interfacial layer;
forming a capping layer over the high-k dielectric layer;
forming a dummy gate electrode layer over the capping layer;
patterning the dummy gate electrode layer, the capping layer, the interfacial layer, and the high-k dielectric layer, wherein, a width of a bottom surface of the patterned dummy gate electrode layer is less than a width of the patterned high-k dielectric layer, and the width of the patterned high-k dielectric layer is less than a width of the patterned interfacial layer;
forming source/drain features adjacent the patterned dummy gate electrode layer;
forming a silicide layer to wrap around the source/drain features;
after the forming of the silicide layer, removing the patterned dummy gate electrode layer and the patterned capping layer to form a gate trench exposing the patterned high-k dielectric layer; and
forming a metal gate electrode in the gate trench and in direct contact with the patterned high-k dielectric layer.
2 . The method of claim 1 , wherein the patterned dummy gate electrode layer has a slanted sidewall surface.
3 . The method of claim 2 , wherein the slanted sidewall surface of the patterned dummy gate electrode layer and the bottom surface of the patterned dummy gate electrode layer forms an acute angle.
4 . The method of claim 2 , wherein a width of the patterned capping layer is less than the width of the patterned interfacial layer.
5 . The method of claim 1 , further comprising:
forming gate spacers along sidewalls of the patterned dummy gate electrode layer and the patterned high-k dielectric layer,
wherein the forming of the metal gate electrode in the gate trench comprises:
forming a work function metal layer in the gate trench, such that sidewall portions of the work function metal layer contacts the gate spacers and a bottom portion of the work function metal layer contacts the high-k dielectric layer; and
forming a bulk conductive layer over the work function metal layer.
6 . The method of claim 5 , wherein a portion of the gate spacers extends along a top surface of the patterned interfacial layer.
7 . The method of claim 5 , wherein a portion of the gate spacers extends along a top surface of the patterned high-k dielectric layer.
8 . A semiconductor structure, comprising:
a high-k metal gate structure (HKMG) over a channel region of a semiconductor layer formed over a substrate, the HKMG comprising:
an interfacial layer disposed over the substrate,
a high-k dielectric layer disposed over the interfacial layer, wherein the high-k dielectric layer and the interfacial layer have different widths, and
a gate electrode disposed over and in physical contact with the high-k dielectric layer, wherein a width of a bottom surface of the gate electrode is less than a width of a top surface of the high-k dielectric layer, and wherein the gate electrode comprises a metal layer and a work function layer extending along a bottom surface and a sidewall surface of the metal layer, the metal layer comprises a shape of a trapezoid in a cross-section view;
a source/drain feature disposed over the substrate and adjacent the HKMG; and
a silicide layer in contact with the source/drain feature,
wherein a portion of the silicide layer is disposed below a top surface of the source/drain feature.
9 . The semiconductor structure of claim 8 , wherein a width of the interfacial layer is greater than a width of the high-k dielectric layer.
10 . The semiconductor structure of claim 9 , wherein the HKMG further comprises:
gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting portions of top surfaces of the high-k dielectric layer and the interfacial layer.
11 . The semiconductor structure of claim 8 , wherein a portion of the silicide layer is disposed laterally adjacent the source/drain feature.
12 . The semiconductor structure of claim 8 , wherein a width of a top surface of the gate electrode is less than the width of the bottom surface of the gate electrode.
13 . The semiconductor structure of claim 8 , wherein an entirety of a sidewall surface of the gate electrode is tilted.
14 . A semiconductor structure, comprising:
a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, the HKMG including:
a high-k dielectric layer, and
a gate electrode disposed over the high-k dielectric layer, wherein the gate electrode has a bottom surface physically in contact with the high-k dielectric layer and a top surface opposite the bottom surface, wherein, in a cross-section view, the top surface spans a first width, and the bottom surface spans a second width greater than the first width;
gate spacers extending along a sidewall surface of the gate electrode and physically contacting a portion of a top surface of the high-k dielectric layer;
source/drain features adjacent the HKMG and comprising a top surface and a sidewall surface above the semiconductor layer; and
a silicide layer extending along the sidewall surface of the source/drain features.
15 . The semiconductor structure of claim 14 , further comprising:
an interlayer dielectric (ILD) layer disposed over the silicide layer; and
a source/drain contact extending through the ILD layer and in direct contact with the silicide layer.
16 . The semiconductor structure of claim 15 ,
wherein the source/drain features coupled to the channel region along a first direction and spans a third width along a second direction substantially perpendicular to the first direction, and the source/drain contact spans a fourth width along the second direction,
wherein the third width is greater than the fourth width.
17 . The semiconductor structure of claim 14 , wherein the gate electrode comprises:
a work function metal layer comprising sidewall portions in direct contact with the gate spacers and a bottom portion in direct contact with the high-k dielectric layer; and
a bulk conductive layer over the work function metal layer.
18 . The semiconductor structure of claim 14 , wherein sidewall portions of the gate spacers are free of the high-k dielectric layer.
19 . The semiconductor structure of claim 14 , wherein each sidewall of the gate electrode forms an acute angle with the high-k dielectric layer.
20 . The semiconductor structure of claim 14 , further comprising:
an interfacial layer disposed between the high-k dielectric layer and the channel region,
wherein a distance between an outer edge of the gate electrode and an outer edge of the high-k dielectric layer is less than a distance between the outer edge of the gate electrode and an outer edge of the interfacial layer.