Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.
1. A method for fabricating a semiconductor device, comprising:
forming a gate structure on a substrate;
forming a contact etch stop layer (CESL) on the gate structure;
forming an interlayer dielectric (ILD) layer on the CESL;
forming a contact plug in the ILD layer and adjacent to the gate structure;
forming a first stop layer on the ILD layer; and
removing the first stop layer and the ILD layer directly on top of the gate structure and the ILD layer between the CESL and the contact plug to form an air gap exposing the CESL after forming the contact plug.
2. The method of claim 1 , further comprising:
forming a spacer adjacent to the gate structure;
forming a source/drain region adjacent to the spacer;
forming the CESL on the gate structure and the source/drain region;
forming the ILD layer on the CESL;
forming the contact plug for connecting the source/drain region;
removing the ILD layer around the gate structure;
forming an inter-metal dielectric (IMD) layer on the first stop layer to form the air gap; and
forming a metal interconnection in the IMD layer.
3. The method of claim 1 , further comprising forming the air gap to expose the contact plug.
4. The method of claim 1 , further comprising:
forming a spacer adjacent to the gate structure;
forming a source/drain region adjacent to the spacer;
forming the CESL on the gate structure and the source/drain region;
forming the ILD layer on the CESL;
forming the contact plug for connecting the source/drain region;
forming a first inter-metal dielectric (IMD) layer on the first stop layer;
forming a metal interconnection in the first IMD layer;
forming a second stop layer on the first IMD layer and the metal interconnection;
forming a hard mask on the second stop layer;
performing a first etching process to remove the hard mask, the second stop layer, the first IMD layer, and the first stop layer;
performing a second etching process to remove the ILD layer;
removing the hard mask; and
forming a second IMD layer on the first IMD layer for forming the air gap.
5. The method of claim 4 , wherein the first etching process comprises a dry etching process.
6. The method of claim 4 , wherein the second etching process comprises a wet etching process.
7. The method of claim 4 , wherein the air gap comprises:
a bottom portion exposing the CESL; and
a top portion exposing the first IMD layer, the second stop layer, and the second IMD layer.
8. The method of claim 4 , wherein the hard mask comprises metal nitride.
9. The method of claim 4 , wherein a thickness of the first stop layer is less than a thickness of the second stop layer.
10. A semiconductor device, comprising:
a gate structure on a substrate;
a contact etch stop layer (CESL) on the gate structure;
an interlayer dielectric (ILD) layer on the CESL;
a contact plug in the ILD layer and adjacent to the gate structure;
a first stop layer on the ILD layer; and
an air gap around the gate structure and between the CESL and the contact plug and exposing the CESL directly on top of the gate structure.
11. The semiconductor device of claim 10 , further comprising:
a spacer adjacent to the gate structure;
a source/drain region adjacent to the spacer;
the CESL on the gate structure and the source/drain region;
the ILD layer on the CESL;
the contact plug for connecting the source/drain region;
an inter-metal dielectric (IMD) layer on the first stop layer; and
a metal interconnection in the IMD layer.
12. The semiconductor device of claim 11 , wherein the air gap exposes the contact plug and the first stop layer.
13. The semiconductor device of claim 10 , further comprising:
a spacer adjacent to the gate structure;
a source/drain region adjacent to the spacer;
the CESL on the gate structure and the source/drain region;
the ILD layer on the CESL;
the contact plug for connecting the source/drain region;
a first inter-metal dielectric (IMD) layer on the first stop layer;
a metal interconnection in the first IMD layer;
a second stop layer on the first IMD layer and the metal interconnection; and
a second IMD layer on the first IMD layer.
14. The semiconductor device of claim 13 , wherein the air gap comprises:
a bottom portion exposing the CESL; and
a top portion exposing the first IMD layer, the second stop layer, and the second IMD layer.
15. The semiconductor device of claim 13 , wherein a thickness of the first stop layer is less than a thickness of the second stop layer.