Syntonization through physical layer of interconnects
In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.
1. A clock syntonization system, comprising:
a first compute node comprising a first physical hardware clock to operate at a first clock frequency;
a second compute node; and
an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to:
derive a second clock frequency from the data rate of the transferred data; and
provide a clock signal at the derived second clock frequency.
2. The system according to claim 1 , wherein the first compute and second compute node may include any one or more of the following: a central processing unit; a graphics processing unit; a network interface controller; a switch; a bridge; and a data processing unit.
3. The system according to claim 1 , wherein the interconnect data bus is a peripheral device interconnect data bus.
4. The system according to claim 1 , wherein the data is transferred over the interconnect data bus in at least one digital signal.
5. The system according to claim 1 , wherein the second compute node includes a second physical hardware clock to operate at a third clock frequency, the clock synchronization circuitry being configured to discipline the second physical hardware clock responsively to a difference between the derived second clock frequency and the third clock frequency.
6. The system according to claim 1 , wherein the second compute node includes a second physical hardware clock, the clock synchronization circuitry being configured to discipline the second physical hardware clock responsively to a difference between the derived second clock frequency and a transmission rate at which data is transferred from the second compute node to the first compute node via the interconnect data bus.
7. The system according to claim 1 , wherein the second compute node includes a second physical hardware clock, the clock synchronization circuitry being configured to discipline the second physical hardware clock of the second compute node responsively to a difference between: the data rate at which the data is received from the first compute node by the second compute node; and a transmission rate at which data is transferred from the second compute node to the first compute node via the interconnect data bus.
8. The system according to claim 1 , wherein the data rate is modulated to spread interference across a range of frequencies so that a variation of the data rate over time describes a modulated signal of frequency against time.
9. The system according to claim 8 , wherein the clock synchronization circuitry includes filtering circuitry to remove modulation from the modulated signal, the clock synchronization circuitry being configured to derive the second clock frequency from the modulated signal with the modulation removed.
10. The system according to claim 8 , wherein the clock synchronization circuitry includes filtering circuitry to digitally remove modulation from the modulated signal, the clock synchronization circuitry being configured to derive the second clock frequency from the modulated signal with the modulation removed.
11. The system according to claim 8 , wherein the clock synchronization circuitry includes filtering circuitry to:
transform the modulated signal yielding a Fourier Transform, and
identify the second clock frequency from the Fourier Transform.
12. The system according to claim 8 , wherein the clock synchronization circuitry is configured to: sample the frequency of the modulated signal yielding multiple frequency values; average the frequency values yielding an average value; and derive the second clock frequency from the average value.
13. The system according to claim 8 , wherein the clock synchronization circuitry is configured to derive the second clock frequency by fitting parameters of a mathematic model of the modulated signal, the parameters including a frequency based on the first clock frequency.
14. The system according to claim 13 , wherein the clock synchronization circuitry is configured to fit the parameters based on performing a regression analysis of the mathematical model.
15. The system according to claim 13 , wherein the clock synchronization circuitry is configured to fit the parameters responsively to using a machine learning model.
16. A clock syntonization method, comprising:
transferring data from a first compute node to a second compute node at a data rate indicative of a first clock frequency of a first physical hardware clock of the first compute node;
deriving a second clock frequency from the data rate of the transferred data; and
providing a clock signal at the derived second clock frequency in the second compute node.
17. The method according to claim 16 , wherein the data is transferred over an interconnect data bus in at least one digital signal.
18. The method according to claim 16 , further comprising disciplining a second physical hardware clock of the second compute node operating at a third clock frequency responsively to a difference between the derived second clock frequency and the third clock frequency.
19. The method according to claim 16 , further comprising disciplining a second physical hardware clock of the second compute node responsively to a difference between the derived second clock frequency and a transmission rate at which data is transferred from the second compute node to the first compute node via an interconnect data bus.
20. The method according to claim 16 , further comprising disciplining a second physical hardware clock of the second compute node responsively to a difference between: the data rate at which the data is received from the first compute node by the second compute node; and a transmission rate at which data is transferred from the second compute node to the first compute node via an interconnect data bus.
21. The method according to claim 16 , further comprising modulating the data rate to spread interference across a range of frequencies so that a variation of the data rate over time describes a modulated signal of frequency against time.
22. The method according to claim 21 , wherein the clock synchronization circuitry includes filtering circuitry to remove modulation from the modulated signal, the clock synchronization circuitry being configured to derive the second clock frequency from the modulated signal with the modulation removed.
23. The method according to claim 21 , further comprising digitally removing modulation from the modulated signal and deriving the second clock frequency from the modulated signal with the modulation removed.
24. The method according to claim 21 , further comprising:
transforming the modulated signal yielding a Fourier Transform; and
identifying the second clock frequency from the Fourier Transform.
25. The method according to claim 21 , further comprising:
sampling the frequency of the modulated signal yielding multiple frequency values;
averaging the frequency values yielding an average value; and
deriving the second clock frequency from the average value.
26. The method according to claim 21 , further comprising deriving the second clock frequency by fitting parameters of a mathematic model of the modulated signal, the parameters including a frequency based on the first clock frequency.
27. The method according to claim 26 , further comprising fitting the parameters based on performing a regression analysis of the mathematical model.
28. The method according to claim 26 , further comprising fitting the parameters responsively to using a machine learning model.