Semiconductor chip with stepped sidewall, semiconductor package including the same, and method of fabricating the same
Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.
1 . A semiconductor chip, comprising:
a substrate including a device region and an edge region;
a device layer and a wiring layer sequentially stacked on the substrate;
a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate;
an upper dielectric stack covering the sub-pad and the residual test pattern;
a bonding pad in the upper dielectric stack and connected to the sub-pad; and
a passivation layer covering the upper dielectric stack,
wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern,
wherein a sidewall of the upper dielectric stack has a stepped region,
wherein a top surface of the bonding pad is at a first depth from a top surface of the passivation layer,
wherein a bottom surface of the stepped region is at a second depth from the top surface of the passivation layer, and
wherein the second depth is about 0.9 times to about 2.0 times the first depth.
2 . The semiconductor chip of claim 1 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of an uppermost one of the upper dielectric layers has the stepped region.
3 . The semiconductor chip of claim 1 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of a lowermost one of the upper dielectric layers is offset from a sidewall of an uppermost one of the upper dielectric layers.
4 . The semiconductor chip of claim 1 , wherein
the device layer includes a device interlayer dielectric layer,
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a surface roughness at a sidewall of an uppermost one of the upper dielectric layers is less than a surface roughness at a sidewall of the device interlayer dielectric layer.
5 . The semiconductor chip of claim 1 , wherein
the wiring layer includes a lower dielectric stack, the lower dielectric stack including a plurality of lower dielectric layers,
the upper dielectric stack includes a plurality of upper dielectric layers,
each of the lower dielectric layers includes a first dielectric material which has a dielectric constant less than a dielectric constant of silicon oxide, and
each of the upper dielectric layers includes a second dielectric material which has a dielectric constant greater than the dielectric constant of the first dielectric material included in each of the lower dielectric layers.
6 . The semiconductor chip of claim 5 , wherein
a portion of the upper dielectric layers penetrates the lower dielectric stack on the edge region to divide the lower dielectric stack into a primary lower dielectric stack and an edge lower dielectric stack,
the primary lower dielectric stack covers the device region and a portion of the edge region, and
the edge lower dielectric stack covers a remaining portion of the edge region.
7 . The semiconductor chip of claim 6 , further comprising:
a guard ring structure in the primary lower dielectric stack, the guard ring structure surrounding the device region, when viewed in a plan view; and
a chipping dam structure in the primary lower dielectric stack, the chipping dam structure surrounding the guard ring structure, when viewed in a plan view.
8 . The semiconductor chip of claim 1 , wherein the sub-pad and the residual test pattern are at a same level and are identical in terms of material and thickness.
9 . The semiconductor chip of claim 1 , further comprising:
a conductive bump penetrating the passivation layer and coupled to the bonding pad; and
a solder layer coupled to the conductive bump.
10 . The semiconductor chip of claim 1 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of an uppermost one of the upper dielectric layers has a square wave shape when viewed in a plan view.
11 . A semiconductor chip, comprising:
a substrate including a device region and an edge region;
a device layer and a wiring layer sequentially stacked on the substrate;
a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate;
an upper dielectric stack covering the sub-pad and the residual test pattern;
a passivation layer on the upper dielectric stack;
a separation dielectric pattern penetrating the wiring layer on the edge region;
a bonding pad in the upper dielectric stack and connected to the sub-pad;
a conductive bump penetrating the passivation layer and coupled to the bonding pad; and
a solder layer coupled to the conductive bump,
wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern,
wherein a sidewall of the upper dielectric stack has a stepped region,
wherein a top surface of the bonding pad is at a first depth from a top surface of the passivation layer,
wherein a bottom surface of the stepped region is at a second depth from the top surface of the passivation layer, and
wherein the second depth is about 0.9 times to about 2.0 times the first depth.
12 . The semiconductor chip of claim 11 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of an uppermost one of the upper dielectric layers has the stepped region.
13 . The semiconductor chip of claim 11 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of a lowermost one of the upper dielectric layers is offset from a sidewall of an uppermost one of the upper dielectric layers.
14 . The semiconductor chip of claim 11 , wherein
the device layer includes a device interlayer dielectric layer,
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a surface roughness at a sidewall of an uppermost one of the upper dielectric layers is less than a surface roughness at a sidewall of the device interlayer dielectric layer.
15 . A semiconductor chip, comprising:
a substrate including a device region and an edge region;
a device layer and a wiring layer sequentially stacked on the substrate;
a residual test pattern and a sub-pad on the wiring layer, the sub-pad being on the device region, the residual test pattern being on the edge region, and a sidewall of the residual test pattern being aligned with a sidewall of the substrate; and
an upper dielectric stack that covers the sub-pad and the residual test pattern,
wherein the upper dielectric stack exposes a portion of a top surface of the residual test pattern,
wherein the device layer includes a device interlayer dielectric layer,
wherein the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
wherein a surface roughness at a sidewall of an uppermost one of the upper dielectric layers is less than a surface roughness at a sidewall of the device interlayer dielectric layer.
16 . The semiconductor chip of claim 15 , wherein the sidewall of the residual test pattern is offset from a sidewall of the upper dielectric stack.
17 . The semiconductor chip of claim 15 , wherein a sidewall of the upper dielectric stack has a stepped region.
18 . The semiconductor chip of claim 15 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of an uppermost one of the upper dielectric layers has a stepped region.
19 . The semiconductor chip of claim 15 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of a lowermost one of the upper dielectric layers is offset from a sidewall of an uppermost one of the upper dielectric layers.
20 . The semiconductor chip of claim 15 , wherein
the upper dielectric stack includes a plurality of upper dielectric layers that are sequentially stacked, and
a sidewall of an uppermost one of the upper dielectric layers has a square wave shape when viewed in a plan view.